If fewer than eight pods are available for timing, the logic analyzer will
truncate the pods allocated. In this case, viewing the logic analyzer
FORMAT menu shows the pod allocations. If the allocations will not
acquire the desired signals, the allocations can be altered manually.
One-card HP 16550A Timing Connections.
Solutions for CPU32
Chapter 3: Connecting and Configuring the Analysis Probe
Connecting the Analysis Probe to the Logic Analyzer
Configuration File (Timing Analysis)
Use configuration files C_33X_1T or C_37X_1T for
timing analysis with the HP 16550A logic analyzer.
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