HP 16600A Series User Manual page 227

Chapter 10: Hardware Reference
Analysis probe signal-to-connector mapping (Timing)
E2480A
CPU32 SIGNAL TIMING
NAME CONNECTOR
PIN
Timing Connector J4, Timing Pod 4
ADDR16 37
ADDR17 35
ADDR18 33
FC0/CS3 31
FC1/CS4 29
FC2/CS5 27
ADDR19/~CS6 25
ADDR20/~CS7 23
ADDR21/~CS8 21
ADDR22/~CS9 19
ADDR23/~CS10 17
na 15
na 13
na 11
~IFetch/DS1 9
~IPipe/DS0 7
~Bkpt/DSclk 5
NOTE: Signals A19—A23 and CS6—CS10 are multiplexed onto the
same pins, and the default configuration of the logic analyzer
assumes that signals A19—A23 are valid. If any of the chip selects,
CS6—CS10, are being used then the bits associated with A19—A23
should be removed from the ADDR label via the format menu in the
logic analyzer. This corresponds to bits 3—7 of pod A4. This results
in the display of correct address information in the ADDR field of
the listing menu and presents only valid address bus bits to the
ADDR field in the trigger menu.
226
ANALYZER TIMING
BIT LABEL
0 ADDR
1 ADDR
2 ADDR
3
4
5
6 ADDR
7 ADDR
8 ADDR
9 ADDR
10 ADDR
11
12
13
14
15
CLK
TIMING
SUBLABEL
PORT A
PORT A
PORT A
PORT C, CSx
PORT C, CSx
PORT C, CSx
PORT C, CSx
PORT C, CSx
PORT C, CSx
PORT C, CSx
PORT C, CSx
Solutions for CPU32