Performance; Encoder Section - Analog Devices AD73360L Manual

DSP CONTROL
D
TO SE
1/2
74HC74
MCLK
CLK
DSP CONTROL
TO RESET
D
1/2
74HC74
MCLK CLK
Figure 19. SE and RESET Sync Circuit for Cascaded
Operation

PERFORMANCE

As the AD73360L is designed to provide high-performance,
low-cost conversion, it is important to understand the means by
which this high performance can be achieved in a typical appli-
cation. This section will, by means of spectral graphs, outline
the typical performance of the device and highlight some of the
options available to users in achieving their desired sample rate,
either directly in the device or by doing some post-processing in
the DSP, while also showing the advantages and disadvantages
of the different approaches.

Encoder Section

The encoder section samples at DMCLK/256, which gives a
64 kHz output rate for DMCLK equal to 16.384 MHz. The
noise-shaping of the sigma-delta modulator also depends on the
frequency at which it is clocked, which means that the best
dynamic performance in a particular bandwidth is achieved by
oversampling at the highest possible rate. If we assume that the
signals of interest are in the bandwidth of dc–4 kHz, then sam-
pling at 64 kHz gives a spectral response which ensures good
SNR performance in that bandwidth, as shown in Figure 20.
0
–20
–40
–60
–80
–100
–120
–140
0 8
FREQUENCY – kHz
Figure 20. FFT (ADC 64 kHz Sampling)
REV. 0
SE SIGNAL SYNCHRONIZED
TO MCLK
Q
RESET SIGNAL SYNCHRONIZED
TO MCLK
Q
SNR = 59.0dB (DC TO f /2)
S
SNR = 78.2dB (DC TO 4kHz)
16 24 32
The sampling rate can be varied by programming the Decimation
Rate Divider settings in CRB. For a DMCLK of 16.384 MHz
sample rates of 64 kHz, 32 kHz, 16 kHz and 8 kHz are available.
Figure 21 shows the final spectral response of a signal sampled
at 8 kHz using the maximum oversampling rate.
0
–20
–40
–60
–80
–100
–120
–140
0
Figure 21. FFT (ADC 8 kHz Internally Decimated from
64 kHz)
It is possible to generate lower sample rates through reducing
the oversampling ratio by programming the DMCLK Rate
Divider Settings in CRB (MCD2-MCD1). This will have the
effect of spreading the quantization noise over a lesser band-
width resulting in a degradation of dynamic performance.
Figure 22 shows a FFT plot of a signal sampled at 8 kHz rate
produced by reducing the DMCLK Rate.
0
–20
–40
–60
–80
–100
–120
–140
0
Figure 22. FFT (ADC 8 kHz Sampling with Reduced
DMCLK Rate)
–21–
AD73360L
SNR = 78dB (DC TO 4kHz)
2
FREQUENCY – kHz
SNR = 72.2dB (DC TO f /2)
S
2
FREQUENCY – kHz
4
4