Analog Devices AD73360L Manual page 12

AD73360L
CONTROL REGISTER B
CONTROL REGISTER C
CONTROL REGISTER D
Table VI. Control Register B Description
7 6 5
C E E MCD2 MCD1
Bit Name Description
0 DR0 Decimation Rate (Bit 0)
1 DR1 Decimation Rate (Bit 1)
2 SCD0 Serial Clock Divider (Bit 0)
3 SCD1 Serial Clock Divider (Bit 1)
4 MCD0 Master Clock Divider (Bit 0)
5 MCD1 Master Clock Divider (Bit 1)
6 MCD2 Master Clock Divider (Bit 2)
7 CEE Control Echo Enable (0 = OFF; 1 = Enabled)
Table VII. Control Register C Description
7 6 5
RES RU PUREF
Bit Name Description
0 GPU Global Power-Up Device (0 = Power Down; 1 = Power Up)
1 Reserved Must Be Programmed to Zero (0)
2 Reserved Must Be Programmed to Zero (0)
3 Reserved Must Be Programmed to Zero (0)
4 Reserved Must Be Programmed to Zero (0)
5 PUREF REF Power (0 = Power Down; 1 = Power Up)
6 RU REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
7 Reserved Must Be Programmed to Zero (0)
Table VIII. Control Register D Description
7 6 5
PUI2 I2GS2 I2GS1
Bit Name Description
0 I1GS0 ADC1:Input Gain Select (Bit 0)
1 I1GS1 ADC1:Input Gain Select (Bit 1)
2 I1GS2 ADC1:Input Gain Select (Bit 2)
3 PUI1 Power Control (ADC1); 1 = ON, 0 = OFF
4 I2GS0 ADC2:Input Gain Select (Bit 0)
5 I2GS1 ADC2:Input Gain Select (Bit 1)
6 I2GS2 ADC2:Input Gain Select (Bit 2)
7 PUI2 Power Control (ADC2); 1 = ON, 0 = OFF
4 3 2
MCD0 SCD1 SCD0
4 3 2
RES RES RES
4 3 2
I2GS0 PUI1 I1GS2
–12–
1 0
DR1 DR0
1 0
RES GPU
1 0
I1GS1 I1GS0
REV. 0