Table 7.5. Expansion Header Pin Information (J6) - Lattice Semiconductor MachXO2 User Manual

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Evaluation Board User Guide
Table 7.4. Expansion Header Pin Information (J6)
Header Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
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20
-4000 Function
VCCIO2
VCCIO2
PB27B
PB26B
PB27A
PB26A
PB24A
PB23D
PB24B
PB23C
GND
GND
PB21B
PB23A
PB21A
PB23B
PB20A
PB18B
PB20B/PCLKC2_1
PB18A
GND
GND
PB15B
PB12B
PB15A
PB12A
PB10A
PB13B/PCLKC2_0
PB10B
PB13A/PCLKT2_0
GND
GND
PB9D
PB7B
PB9C
PB7A
PB6B
PB3A
PB6A
PB3B
-6900C Function MachXO2/MachXO3 Ball
VCCIO2
VCCIO2
PB35B
PB34B
PB35A
PB34A
PB31A
PB28B
PB31B
PB28A
GND
GND
PB26B
PB29A
PB26A
PB29B
PB23A/PCLKT2_1
PB21B
PB23B/PCLKC2_1
PB21A
GND
GND
PB18B
PB15B
PB18A
PB15A
PB13A
PB16B/PCLKC2_0
PB13B
PB16A/PCLKT2_0
GND
GND
PB10B
PB9B
PB10A
PB9A
PB7B
PB4A
PB7A
PB4B
K8,K9,N5,N12
K8,K9,N5,N12
T12
T14
R11
R13
T11
M11
P11
N10
—
—
T10
P10
R9
R10
T9
N9
P9
M8
—
—
T8
L8
P8
M6
R7
R8
P7
T7
—
—
L7
R6
N6
T5
R4
P4
T3
T4
FPGA-EB-02036-1.4