Figure A.6. Bank 2 I/O - Lattice Semiconductor MachXO2 User Manual

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Evaluation Board User Guide
5
IO_P4
IO_T4
D
NOTE : PLACE R84,R81,R83,R85 CLOSE TO U5
CSSPIN 0 R84
IO_T3
IO_R4
IO_T5
IO_R6
IO_N6
IO_L7
MCLK 0 R81
SPISO 0 R83
IO_R7
IO_P7
C
IO_M6
IO_L8
IO_T7
IO_R8
IO_P8
IO_T8
VCCIO2
C35
C36 C37
0.01uF 0.1uF 0.1uF
B
NOTE : PLACE TEST POINTS NEAR PIN 1 OF J7 AND THE SAME LINE
Sheet[2] USB_I2C_EN
Sheet[2] FTDI_SDA
Sheet[2] FTDI_SCL
Sheet[4] SDA
Sheet[4] SCL
SN
SPISO
SISPI
MCLK
A
SDA
SCL
5
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34
4
U5C
BANK2
P4 M8 IO_M8
PB3A/PB3A/PB4A PB16C/PB18A/PB21A
T4 N9 IO_N9
PB3B/PB3B/PB4B PB16D/PB18B/PB21B
IO_T9
T2 T9
PB3C/PB3C/PB4C PB16A/PB20A/PB23A || PCLKT2_1
IO_P9
R3 P9
PB3D/PB3D/PB4D PB16B/PB20B/PB23B || PCLKC2_1
R5 R9 IO_R9
PB5A/PB4A/PB6A || CSSPIN PB18A/PB21A/PB26A
P5 T10 IO_T10
PB5B/PB4B/PB6B PB18B/PB21B/PB26B
T3 M9
PB6C/PB6A/PB7A PB18C/PB21C/PB26C
R4 L10
PB6D/PB6B/PB7B PB18D/PB21D/PB26D
T5 N10 IO_N10
PB6A/PB7A/PB9A PB19C/PB23C/PB28A
R6 M11 IO_M11
PB6B/PB7B/PB9B PB19D/PB23D/PB28B
N6 P10 IO_P10
PB8C/PB9C/PB10A PB19A/PB23A/PB29A
IO_R10
L7 R10
PB8D/PB9D/PB10B PB19B/PB23B/PB29B
P6 T11 IO_T11
PB21A/PB24A/PB31A
PB8A/PB9A/PB12A || MCLK/CCLK
T6 P11 IO_P11
PB21B/PB24B/PB31B
PB8B/PB9B/PB12B || SO/SPISO
R7 M10
PB21C/PB24C/PB31C
P7 PB9A/PB10A/PB13A N11
PB21D/PB24D/PB31D
PB9B/PB10B/PB13B
M7
N7 R13 IO_R13
PB9C/PB10C/PB13C
PB22C/PB26A/PB34A
T14 IO_T14
PB9D/PB10D/PB13D
PB22D/PB26B/PB34B
M6
IO_R11
L8 R11
PB11C/PB12A/PB15A
PB22A/PB27A/PB35A
T12 IO_T12
PB11D/PB12B/PB15B
PB22B/PB27B/PB35B
T7 P12
PB24A/PB29A/PB37A
R8 T13
PB24B/PB29B/PB37B
PB11A/PB13A/PB16A || PCLKT2_0
PB11B/PB13B/PB16B || PCLKC2_0
P8 R12 SN
PB12A/PB15A/PB18A PB25A/PB30A/PB38A || SN
T8 P13
PB12B/PB15B/PB18B PB25B/PB30B/PB38B || SI/SISPI
N8 T15
PB12C/PB15C/PB18C PB25C/PB30C/PB38C
L9 R14
PB12D/PB15D/PB18D PB25D/PB30D/PB38D
K8 N5
VCCIO2/VCCIO2/VCCIO2 VCCIO2/VCCIO2/VCCIO2
K9 N12
VCCIO2/VCCIO2/VCCIO2 VCCIO2/VCCIO2/VCCIO2
C38
1K-2K/4K/7K || 2nd_Fn. 0.1uF
LCMXO3L-6900C-5BG256C
1
TP15
1 TP14
1 TP13
1
2
J7
3
4 DNI
5
6 NOTE : PLACE J7 NEAR J1
CSSPIN 0
CON6
FTDI_SDA
0 DNI TP12
R91
0 DNI FTDI_SCL
R92
4

Figure A.6. Bank 2 I/O

3
NOTE : MAKE PWR TRACES
CAPABLE OF 1A
VCCIO2 VCCIO2
J6
2 1
IO_T14 4 3
IO_R13 6 5
8 7
IO_M11
9
IO_N10 10
12 11
IO_P10 14 13
IO_R10
16 15
IO_N9
18 17
IO_M8 20 19
22 21
IO_L8 24 23
IO_M6 26 25
IO_R8 28 27
IO_T7
30 29
32 31
IO_R6 34 33
IO_T5 36 35
IO_P4 38 37
IO_T4 40 39
VCCIO2
Header 2x20
NOTE : ROUTE J6 TRACES AS 100OHMS, LENGTH MATCHED
DIFFERENTIAL PAIRS
R80
10K
0 R85 SISPI
VCCIO2
C39 C40
0.1uF 0.1uF
+3.3V
NOTE : PLACE SPI FLASH IN THE BOTTOM SIDE
C41
R63
100nF
10V
R64 R65 R66
1K U6
SISPI 5 2 SPISO 10K 10K 10K
SDI SDO
MCLK 6
SCK
3
WP
SPI FLASH
R67 1 7
CS HOLD
S25FL204K0TMFI041
1
3
2
IO_P4 R46 DNI
IO_T4 100
IO_T3 R47 DNI
IO_T12 IO_R4
100
IO_R11
IO_T11 IO_T5 R48 DNI
IO_P11 IO_R6 100
IO_T10 IO_N6 R49 DNI
IO_R9 IO_L7
100
IO_T9
IO_P9
IO_R7 R50 DNI
IO_T8 IO_P7 100
IO_P8
IO_R7 IO_M6
R51 DNI
IO_P7 IO_L8
100
IO_L7 IO_T7 R52 DNI
IO_N6 IO_R8 100
IO_R4
IO_T3 IO_P8
R53 DNI
IO_T8
100
IO_M8 R54 DNI
IO_N9 100
IO_T9
R55 DNI
IO_P9 100
IO_R9 R56 DNI
IO_T10 100
IO_N10
R57 DNI
IO_M11 100
IO_P10 R58 DNI
IO_R10 100
IO_T11
R59 DNI
IO_P11 100
IO_R13 R60 DNI
IO_T14 100
IO_R11
R61 DNI
IO_T12
100
NOTE : PLACE ALL THE LVDS DIFF TERMINATION
RESISTORS IN TOP AND CLOSE TO U5
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Phone (503) 268-8001 -or- (800) LATTICE
Title
BANK2 I/O
Size
Project
MACHXO3 Starter Kit - LCMXO3L-6900C
B
Date: 12-SEP-2014
2
1
D
C
B
A
Schematic Rev 1.0
Board Rev
A
Sheet 6 of 8
1
FPGA-EB-02036-1.4