Table 6.1
describes the components on the board and the interfaces it supports.
Table 6.1. Starter Kit Components and Interfaces
Component/Interface
Circuits
USB Controller
USB Mini-B Socket
Components
LCMXO2, LCMXO3L, or
LCMXO3LF
Interfaces
LED Array
Push Button Switch
4-position DIP Switch
Four 2 x 20 Header
Landings
1 x 8 Header Landing
1 x 6 Header Landing
4 x 10 40-Hole Prototype
Area
Test Points
Run the Demonstration Design
Upon power-up, the pre-programmed demonstration design automatically loads and drives the LED array in a 1-hertz
pattern. The program shows a clock divider driven either by the MachXO2/MachXO3 internal oscillator or the external
FTDI clock chip. The divider modules (heartbeat.v and kitcar.v) are clocked at the default frequency of 12 MHz which
divides the clock to cycle the LED display approximately once per second. The resulting light pattern is determined by
the DIP Switch (SW2) setting as shown in
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FPGA-EB-02036-1.4
Schematic
Type
Reference
Circuit
U1: FT2232H
I/O
J2:USB_MINI_B
FPGA
U5: LCMXO2-
4000ZE-1BG256C,
LCMXO3L-6900C-
5BG256C or
LCMXO3LF-
6900C-5BG256C
Output
D9-D2
Input
SW1
Input
SW2
I/O
J3: header_2x20
J4: header_2x20
J6: header_2x20
J8: header_2x20
I/O
J1: header_1x8
I/O
J7: header_1x6
—
—
Power
TP1: +3.3 V TP2:
+1.2 V TP3: GND
Table
6.2.
MachXO3
XO3 L_SK_b li nk.v
OSCH
12.09 MHz
X1
12.0 M Hz
SW2
4-Pos iti on DIPSW
SW1
Async Res et
Mo mentary P B
Figure 6.2. Demonstration Design Block Diagram
MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Description
USB-to-JTAG interface and dual USB UART/FIFO IC
Programming and debug interface
4000-LUT and 6900-LUT devices are in a 14 mm x 14 mm,
256-ball caBGA package.
Red LEDs
Momentary User Input
User inputs
User-definable I/O
Optional JTAG interface
2
Optional SPI/I
C interfaces
Prototype area 100 mil centered holes.
Power and ground reference points
Ki tcar .v
1 x 8
LED
Array
Heartbe at.v
Evaluation Board User Guide
13
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