I²C Control Port; Figure 10.Dac Dc Loading - Cirrus Logic CS4244 Manual

and 17, the VQ voltage will never rise to its minimum operating voltage. If the VQ voltage never rises
above this minimum operating voltage, the device will not finish the power-up sequence and normal op-
eration will not begin.
Also note that any AOUTx± pin(s) with a DC load must remain powered up (PDN DACx = 0) to keep the
VQ net at its nominal voltage during normal operation, otherwise clipping may occur on the outputs.
Note that the load capacitors (CL
on the VQ net during power-up will affect the amount of time it takes for the VQ voltage to rise to its nom-
inal operating voltage after VA power is applied. The time period can be calculated using the time constant
given by the internal series resistor and the load capacitors.
4.3 I²C Control Port
All device configuration is achieved via the I²C control port registers as described in the
cations - Control Port
to the audio sample rates. However, to avoid potential interference problems, the I²C pins should remain
static if no operation is required. The CS4244 acts as an I²C slave device.
SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. The AD0 and
AD1 pins form the two least significant bits of the chip address and should be connected through a resistor
to VL or GND as desired. The SDOUT2 pin is used to set the AD2 bit by connecting a resistor from the SD-
OUT2 pin to VL or to GND. The state of these pins are sensed after the
DS900F2
) are also in parallel during power-up. The amount of total capacitance
x
VA
~140kΩ
VQ
NET
External VQ
~140kΩ
capacitor
Figure 10. DAC DC Loading
table. The operation via the control port may be completely asynchronous with respect
AOUT1+
RL
CL
1+ 1+
S1±
AOUT1-
RL CL
1- 1-
AOUT2+
RL CL
2+
2+
S2±
AOUT2-
RL CL
2-
2-
AOUT3+
RL CL
3+ 3+
S3±
AOUT3-
RL
CL
3-
3-
AOUT4+
RL
CL
4+
4+
S4±
AOUT4-
RL
CL
4- 4-
CS4244
CS4244
Switching Specifi-
is released from reset.
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