Clock & Sp Select (Address 06H) - Cirrus Logic CS4244 Manual

6.3 Clock & SP Select (Address 06h)
7 6
BASE RATE[1:0]
6.3.1 Base Rate Advisory
Advises the CS4244 of the base rate of the incoming base rate. This allows for the de-emphasis filters to
be adjusted appropriately. The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz
base rates. It is not supported for 96 kHz or for any settings in Double Speed Mode.
BASE RATE
00
01
10
11
6.3.2 Speed Mode
Sets the speed mode in which the CS4244 will operate..
SPEED MODE
00
01
10
11
6.3.3 Master Clock Rate
Sets the rate at which the master clock is entering the CS4244. Settings are given in "x" multiplied by the
incoming sample rate, as MCLK must scale directly with incoming sample rate.
MCLK RATE
000
001
010
011
100
101
110
111
DS900F2
5 4
SPEED MODE[1:0]
Base Rate is:
48 kHz
44.1 kHz
32 kHz
Reserved
Speed Mode is:
Single Speed Mode
Double Speed Mode
Reserved
Auto Detect (Slave Mode only)
MCLK is:
256xF in Single Speed Mode or 128xF
S
384xF in Single Speed Mode or 192xF
S
512xF in Single Speed Mode or 256xF
S
Reserved
Reserved
Reserved
Reserved
Reserved
3 2
MCLK RATE[2:0]
in Double Speed Mode
S
in Double Speed Mode
S
in Double Speed Modex
S
CS4244
1 0
Reserved
48