Interrupt Mask 1 (Address 1Fh) - Cirrus Logic CS4244 Manual

6.16

Interrupt Mask 1 (Address 1Fh)

7 6
MASK MASK
TST MODE ERR SP ERR
6.16.1 Test Mode Error Interrupt Mask
Controls whether a Test Mode Error event flags the interrupt pin. A test mode error occurs when an inad-
vertent I²C write places the device in test mode.
MASKTSTMOD ERR In the event of a Test Mode Error event, Interrupt Pin will:
0
1
6.16.2 Serial Port Error Interrupt Mask
Controls whether the interrupt pin if flagged when any of the following parameters are changed without
first powering down the device (i.e., setting all
• Serial Port Format:
• Speed Mode:
device, flags this error and the Clocking Error. In master mode, changing MCLK frequency without the
device being powered down does not flag this or the Clocking Error since MCLK/F
• Master/Slave:
MASK SP ERR
0
1
6.16.3 Clocking Error Interrupt Mask
Allows or prevents a Clocking Error event from flagging the interrupt pin. See
MASK CLK ERR
0
1
6.16.4 ADCx Overflow Interrupt Mask
Allows or prevents an ADCx Overflow event from flagging the interrupt pin.
MASK ADCx OVFL In the event of an ADCx Overflow event, Interrupt Pin will:
0
1
DS900F2
5 4
MASK CLK ERR Reserved
Be Flagged
Not be flagged
SP FORMAT[1:0]
SPEED MODE (In slave mode, changing the MCLK/F
MSTR/SLV
In the event of a Serial Port Error event, Interrupt Pin will:
Be Flagged
Not be flagged
In the event of a Clocking Error event, Interrupt Pin will:
Be Flagged
Not be flagged
Be Flagged
Not be flagged
3 2
MASK MASK
ADC4 OVFL ADC3 OVFL
Power Down ADCx and
CS4244
1
MASK
ADC2 OVFL ADC1 OVFL
Power Down DACx bits):
ratio without powering down the
S
does not change.)
S
Section 4.8 for details.
0
MASK
56