Figure 23.Adc Path - Cirrus Logic CS4244 Manual

4.6.2 ADC Path
AIN1 (±)
AIN2 (±)
AIN3 (±)
AIN4 (±)
VL
1.8 to 5.0 VDC
4.6.2.1 Analog Inputs
AINx+ and AINx- are line-level differential analog inputs. The analog input pins do not self-bias and must
be externally biased to VA/2 to avoid clipping of the input signal. The full-scale analog input levels are
scaled according to VA and can be found in the Analog Input Characteristics tables on pages
The ADC output data is in two's complement binary format. For inputs above positive full scale or below
negative full scale, the ADC will output 7FFFFFH or 800000H, respectively, and cause the ADC Overflow
bit in the Interrupt Notification 1
4.6.2.2 Active ADC Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK = 12.288 MHz). The digital filter
will reject signals within the stopband of the filter. However, there is no rejection for input signals which
are multiples of the digital passband frequency (n
a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to pro-
viding the optimum source impedance for the modulators. The use of capacitors that have a large voltage
coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity.
DS900F2
Multi-bit
 ADC
Channel Volume ,
Mute, Invert,
Digital Filters
Noise Gate
Serial Audio Interface
SDOUT1 SDOUT2 SDIN2 SDIN1
register to be set to a '1'.
VD VA
2.5 VDC 5.0 VDC
2.5 V
LDO Analog Supply
Master
Volume
Control Interpolation
Filter
Level Translator
Frame Sync
Master Clock In
Clock / LRCK
Figure 23. ADC Path

6.144 MHz), where n = 0,1,2,... Refer to
DAC &
Multi-bit 
Analog
Modulators
Filters
Control Port
Serial Clock
2
INT I C Control
RST
In/ Out
Data
CS4244
AOUT1 (±)
AOUT2 (±)
AOUT3 (±)
AOUT4 (±)
12 and 13.
Figure 24 for
35