I/O Pin Characteristics - Cirrus Logic CS4244 Manual

VA 20
VQ 22
VREF 23
VBIAS 24
25,27,29,
AOUTx-
31
26,28,30,
AOUTx+
32
TSTOx 33,34
RST 35
INT 36
AD2/SDOUT2 37
AD1 38
AD0 39
SCL 40
GND -
1.1

I/O Pin Characteristics

Input and output levels and associated power supply voltage are shown in the table below. Logic levels
should not exceed the corresponding power supply voltage.
Power Supply
VL
AD2/SDOUT2 Input/Output 5.0 V CMOS
Notes:
1. Internal connection valid when device is in reset.
2. This pin has no internal pull-up or pull-down resistors. External pull-up or pull-down resistors should
be added in accordance with
DS900F2
Analog Power (Input) - Positive power for the analog sections.
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
Analog Power Reference (Input) - Return pin for the VBIAS cap.
Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs.
Negative Analog Output (Output) - Negative output signals from the internal digital to analog con-
verters. The full scale analog output level is specified in the
on pages 16 and 17
.
Positive Analog Output (Output) - Positive output signals from the internal digital to analog convert-
ers. The full scale analog output level is specified in the
pages 16 and 17
.
Test Outputs (Output) - Test outputs. These pins should be left unconnected.
Reset (Input) - Applies reset to the internal circuitry when pulled low.
Interrupt (Output) - Sent to DSP to indicate an interrupt condition has occurred.
I²C Address Bit 2/Serial Data Output 2 (Input/Output) - Sets the I²C address bit 2 at reset. Func-
tions as Serial Data Out 2 for AIN3 and AIN4 ADC data output in Left Justified and I²S modes. High
impedance in TDM mode. See
operation.
I²C Address Bit 1 (Input) - Sets the I²C address bit 1.
I²C Address Bit 0 (Input) - Sets the I²C address bit 0.
Serial Control Port Clock (Input) - Serial clock for the I²C control port.
Thermal Pad - The thermal pad on the bottom of the device should be connected to the ground
plane via an array of vias.
Pin Name I/O
SCL Input
SDA Input/Output
INT Output
Input
RST
MCLK Input
FS/LRCK Input/Output 5.0 V CMOS Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
SCLK Input/Output 5.0 V CMOS Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
SDOUT1 Output
SDINx Input
AD0,1 Input
Figure
Section 4.3 I²C Control Port
Internal Connections
Driver
(Note 1)
- Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
CMOS/Open
Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
Drain
CMOS/Open
(Note 2)
Drain
- (Note 2)
- Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
5.0 V CMOS Weak Pull-down (~500k
- Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis
- (Note 2)
(Note 2)
2.
Analog Output Characteristics tables
Analog Output Characteristics tables on
for more details concerning this mode of
Receiver
5.0 V CMOS, with Hysteresis
5.0 V CMOS
5.0 V CMOS
CS4244
-
6