Sample Width Select (Address 07H); Serial Port Control (Address 08H) - Cirrus Logic CS4244 Manual

6.4

Sample Width Select (Address 07h)

7 6
SDOUTx SW[1:0]
6.4.1 Output Sample Width
These bits set the width of the samples placed into the outgoing SDOUTx streams.
OUTPUT SW
00
01
10
11
Note: Bits wider than the Output Sample Width setting are cleared within the SDOUTx data stream.
6.4.2 Input Sample Width
These bits set the width of the samples coming into the CS4244 through the SDINx TDM streams.
INPUT SW
00
01
10
11
Note: In Left Justified or I²S mode, the Input Sample Width is fixed to 24 bits.
6.5

Serial Port Control (Address 08h)

7 6
INV SCLK
6.5.1 Invert SCLK
When set, this bit inverts the polarity of the SCLK signal.
INV SCLK
0
1
6.5.2 Serial Port Format
Sets the format of both the incoming serial data signals and outgoing serial data signals.
SP FORMAT
00
01
10
11
DS900F2
5 4
INPUT SW[1:0]
Sample Width is:
16 bits
18 bits
20 bits
24 bits
Sample Width is:
16 bits
18 bits
20 bits
24 bits
5 4
Reserved[2:0]
SCLK is:
Not Inverted
Inverted
Format is:
Left Justified
I²S
TDM (Slave Mode Only)
Reserved
3 2
Reserved[1:0]
3 2
SP FORMAT[1:0]
CS4244
1 0
Reserved[1:0]
1 0
SDO CHAIN MASTER/
SLAVE
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