Tektronix AWG7000 Series Service Manual page 29

CLK10G Board
AWG10G Board
AWG7000 Series Service Manual
The CLK10G board provides a 5 GHz to 10 GHz clock to the AWG10G board.
Two clock outputs go to the CH1 and CH2 DAC. The clock output to CH2 should
be terminated for 1 channel models. The clock input accepts 5GHz to 10 GHz clock
signals from an external signal source. The reference clock input accepts 5 MHz to
800 MHz reference clock signals from an external signal source. The 10 MHz
reference output can be used for synchronizing frequency between two or more
instruments. The CLK10G board consists of the following blocks:
YIG oscillator (5GHz to 10 GHz)
Fractional-N PLL
10.0 MHz TCXO (reference oscillator)
The AWG10G board generates arbitrary waveforms based on the waveform
memory and the sequence memory. There are two types of PLDs (Xilinx FPGA)
on the board. One is an AWG controller called PLD131 which interfaces to/from
the MIO board. The other is a memory controller called PLD130 which generates
waveform patterns. Waveform data is stored in ZBT type SRAMs. The sequence
memory is included in the memory controller PLD. The AWG10G board consists
of the following blocks:
10 GS/s DAC (HFD205 ASIC)
8 channels 8:1 MUX (TEK0015 ASIC)
PLD130 (Xilinx Virtex-2 FPGA) as a memory controller
PLD131 (Xilinx Virtex-2 FPGA) as an AWG controller
ZBT type SRAM for the waveform memory
Inter-channel phase detector
Trigger and event inputs
DC Output
DC-DC converter (1.5 V and 2.5 V power supply)
Theory of Operation
2-5