Alinx ZYNQ7000 FPGA User Manual page 22

Figure 6-4: 50Mhz active crystal oscillator on the AX7350B
PL Clock pin assignment:
DDR Reference Clock
A 200MHz differential crystal oscillator is provided to bank34 as the
reference clock of the DDR controller of PL;
Figure 6-3 200Mhz active crystal oscillator for DDR
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ZYNQ FPGA Development Board AX7350B User Manual
Signal Name
CLK_50MHZ
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board
ZYNQ Pin
J14