Alinx ZYNQ7000 FPGA User Manual page 23

PL Clock Pin Assignment:
Transceiver Reference Clock
One 156mhz differential crystal oscillator is provided to bank111 as the
reference clock of SPF of GTX transceiver; In addition, two channels of
100MHz differential reference clock are generated by the dsc557-0334fi1 chip
and provided to the bank112 and PCIe socket respectively. The schematic
diagram of the reference circuit design is shown in the following figure:
ZYNQ
Programmable clock source ZYNQ pin assignment:：
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ZYNQ FPGA Development Board AX7350B User Manual
Signal Name
CLK0_P
CLK0_N
U1
BANK
111
BANK
112
P1
PCIE
PCIE_REFCLK_P/N
插槽
Figure 6-4 Programmable clock source
Signal Name
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ZYNQ
C8
C7
SFP_CLK0_P/N
PCIE_CLK0_P/N
CLK0+
CLK1+
ZYNQ
Pin
156.25M
hz
U51
CLK0-
CLOCK
DSC557-0334FI1
CLK1-
Pin