Part 4: 50M Active Crystal - Alinx AX301 User Manual

FPGA Development Board AX301 User Manual
Figure 3-5: FPGA GND Pin

Part 4: 50M Active Crystal

Figure 4-1 is a 50M active crystal circuit that provides a clock source for
the development board. Crystal output is connected to FPGA global input clock
pin (CLK1 pin E1). This CLK1 can be used to drive the user logic circuit in the
FPGA. The user can configure the FPGA's internal PLL (Phase Locked Loop)
to divide and multiply to achieve clocks of other frequencies.
Figure 4-1: 50M Active Crystal Circuit
Figure 4-2: 50M Active Crystal on the FPGA Board
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