Part 6: Clock Configuration - Alinx ZYNQ7000 FPGA AC7021B User Manual

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Pin Assignment of eMMC Flash
Signal Name
MMC_CCLK
MMC_CMD
MMC_D0
MMC_D1
MMC_D2
MMC_D3

Part 6: Clock configuration

The AC7021B core board provides active clocks for the PS system and the
PL logic sections, respectively, so that the PS system and the PL logic can
work independently.
PS system clock source
The ZYNQ chip provides a 33.333 MHz clock input to the PS section
through the X1 crystal on the development board. The input of the clock is
connected to the pins of PS_CLK_500 of the BANK500 of the ZYNQ chip. The
schematic diagram is shown in Figure 6-1:
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ZYNQ FPGA Development Board AC7021B User Manual
Figure 5-2: eMMC Flash on the Core Board
Table 5-2: Pin Assignment of eMMC FLASH
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ZYNQ Pin Name
PS_MIO48_501
PS_MIO47_501
PS_MIO46_501
PS_MIO49_501
PS_MIO50_501
PS_MIO51_501
Pin Number
D11
B10
D12
C14
D13
C10