Part 4 Qspi Flash - Alinx ZYNQ7000 FPGA AC7021B User Manual
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Also See for ZYNQ7000 FPGA AC7021B:
- User manual (61 pages) ,
- User manual (40 pages) ,
- User manual (46 pages)
Table of Contents
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DDR3_A9
DDR3_A10
DDR3_A11
DDR3_A12
DDR3_A13
DDR3_A14
DDR3_BA0
DDR3_BA1
DDR3_BA2
DDR3_S0
DDR3_RAS
DDR3_CAS
DDR3_WE
DDR3_ODT
DDR3_RESET
DDR3_CLK0_P
DDR3_CLK0_N
DDR3_CKE
Part 4 QSPI Flash
The core board is equipped with a 256MBit Quad-SPI FLASH chip, model
W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the non-
volatile nature of QSPI FLASH, it can be used as a boot device for the system
to store the boot image of the system. These images mainly include FPGA bit
files, ARM application code, and other user data files. The specific models and
related parameters of QSPI FLASH are shown in Table 4-1.
Position
U7
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure 4-1
shows the QSPI Flash in the schematic.
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ZYNQ FPGA Development Board AC7021B User Manual
PS_DDR_A9_502
PS_DDR_A10_502
PS_DDR_A11_502
PS_DDR_A12_502
PS_DDR_A13_502
PS_DDR_A14_502
PS_DDR_BA0_502
PS_DDR_BA1_502
PS_DDR_BA2_502
PS_DDR_CS_B_502
PS_DDR_RAS_B_502
PS_DDR_CAS_B_502
PS_DDR_WE_B_502
PS_DDR_ODT_502
PS_DDR_DRST_B_502
PS_DDR_CKP_502
PS_DDR_CKN_502
PS_DDR_CKE_502
Table 3-2: DDR3 DRAM Pin Assignment
Model
W25Q256FVEI
Table 4-1: QSPI FLASH Specification
Amazon Store: https://www.amazon.com/alinx
Capacity
32M Byte
H5
J3
G5
H4
F4
G4
L7
L6
M6
P6
R5
P3
R4
P5
F3
N4
N5
V3
Factory
Winbond
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