Figure 17.I²S Serial Audio Formats; Figure 18.Left-Justified Serial Audio Formats - Cirrus Logic CS44600 Manual

4.4.1.1 I²S Data Format
For I²S, data is received most significant bit first, one DAI_SCLK delay after the transition of DAI_LRCK,
and is valid on the rising edge of DAI_SCLK. For the I²S format, the left channel data is presented when
DAI_LRCK is low; the right channel data is presented when DAI_LRCK is high.
DAI_LRCK
DAI_SCLK
-1 -2 -3 -4 -5
DAI_SDINx MSB
4.4.1.2 Left-Justified Data Format
For left-justified format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK
transition and is valid on the rising edge of DAI_SCLK. For the left-justified format, the left channel data
is presented when DAI_LRCK is high and the right channel data is presented when DAI_LRCK is low.
DAI_LRCK
DAI_SCLK
-1 -2 -3 -4 -5
DAI_SDINx MSB
DS633F1
Left C hannel
+5 +4 +3 +2 +1
LSB
I²S Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample
16
18 to 24
Figure 17. I²S Serial Audio Formats
Left Channel
+5 +4 +3 +2 +1
LSB
Left-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample SCLK Rate(s)
16 32, 48, 64, 128, 256 Fs
18 to 24 48, 64, 128, 256 Fs
Figure 18. Left-Justified Serial Audio Formats
-1 -2 -3 -4
MSB
SCLK Rates
32, 48, 64, 128, 256 Fs
48, 64, 128, 256 Fs
-1 -2 -3 -4
MSB
CS44600
R ig ht C ha nnel
+5 +4 +3 +2 +1
LSB
Right Channel
+5 +4 +3 +2 +1
LSB
27