1. Manuals
  2. Brands
  3. Cirrus Logic Manuals
  4. Controller
  5. Crystal LAN CS8900A
  6. Reference manual

Cirrus Logic Crystal LAN CS8900A Reference Manual

Ethernet controller
Hide thumbs Also See for Crystal LAN CS8900A:
Table of Contents

Advertisement

Quick Links

Download this manual
AN83
Application Note
&U\VWDO /$1ΠCS8900A ETHERNET CONTROLLER
TECHNICAL REFERENCE MANUAL
By Deva Bodas
Revised by James Ayres
Cirrus Logic, Inc.
Copyright  Cirrus Logic, Inc. 2001
P.O. Box 17847, Austin, Texas 78760
JUN '01
(All Rights Reserved)
(512) 445 7222 FAX: (512) 445 7581
AN83REV3
http://www.cirrus.com
1

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Crystal LAN CS8900A and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Cirrus Logic Crystal LAN CS8900A

Summary of Contents for Cirrus Logic Crystal LAN CS8900A

  • Page 1 &U\VWDO /$1Œ CS8900A ETHERNET CONTROLLER TECHNICAL REFERENCE MANUAL By Deva Bodas Revised by James Ayres Cirrus Logic, Inc. Copyright  Cirrus Logic, Inc. 2001 P.O. Box 17847, Austin, Texas 78760 JUN ‘01 (All Rights Reserved) (512) 445 7222 FAX: (512) 445 7581 AN83REV3 http://www.cirrus.com...

  • Page 2: Table Of Contents

    (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture...
  • Page 3 AN83 LOW COST ETHERNET COMBO CARD REFERENCE DESIGN: CRD8900 ..........21 General Description ..........................21 Board Design ............................21 Crystal Oscillator ..........................21 ISA Bus Interface ..........................21 External Decode Logic ........................21 EEPROM............................21 Socket for Optional Boot PROM ..................... 21 LEDs ...............................

  • Page 4: Schematic Checklist

    The schematic checklist and the example connec- EEDataIn should be pulled to ground if not used. tion diagrams to the Hitachi SH3, Cirrus Logic CL- 10Base-T circuit -- no caps on TX lines between PS7211 and the Motorola MC68302 microproces- isolation transformer and 10 Base-T connector.

  • Page 5: Software Checklist

    AN83 SOFTWARE CHECKLIST After a software or hardware reset, always wait until the SelfStatus register, bit 7 (INITD) is set When servicing the interrupt always read the before reading or writing any other registers. Interrupt Status Queue (ISQ) first. Process that Allow only one transmit in progress at any given individual event before reading the ISQ again.

  • Page 6: Introduction To Cs8900A Technical Reference Manual

    AN83 INTRODUCTION TO CS8900A As shown in the Figure 1, the CS8900A requires a TECHNICAL REFERENCE MANUAL minimum number of external components. The EEPROM stores configuration information such as This Technical Reference Manual provides the in- interrupt number, DMA channel, I-O base address, formation which will be helpful in designing a memory base address, and IEEE Individual Ad- board using the CS8900A, programming the asso-...

  • Page 7: Hardware Design

    CS8900A to non-Intel and non ISA sys- and call also store state/configuration information tems. Design examples include the MC68302, for the driver. Cirrus Logic CL-PS7211 ARM and Hitachi SH3. Cirrus’s Software Driver (&U\VWDO /$1Œ) Distribu- The CS8900A Architecture tion Policy is as follows. The CS8900A developer...

  • Page 8: Isa Bus

    AN83 ISA Bus In memory mode, all the internal registers of the CS8900A can be accessed directly via memory An ISA bus is a simple, asynchronous bus that can reads/writes. Please refer to the CS8900A easily be made to interface to most synchronous or datasheet for the memory address map.

  • Page 9: Selection Of I/O, Memory And Dma Modes

    AN83 long as the CS8900A contains frames completely 1) If an EEPROM is not used in the Ethernet de- received. If ‘n’ words are to be transferred from the sign, the application can address the CS8900A CS8900A to the system RAM, the DRQ signal re- in IO mode (0300h) in order to enable memory mains active until the (n-1) word is transferred.

  • Page 10: Read And Write Signals

    AN83 When the MC68302 generates address 0D00300h, generated unless the address on the address bus is the address seen by the CS8900A will be 00300h stable. Further, for an access in memory mode, an with one of the IO commands (IOR or IOW) active. IO command is not active.

  • Page 11: Status Signals From Cs8900A

    AN83 Status Signals from CS8900A MHz clock available in the system, it can be con- nected to the XTL1 (pin 97) pin of the CS8900A. There are several status signals that are output from It is important that this clock be TTL or CMOS the CS8900A, such as IOCHRDY, IOCS16, with 40/60 duty cycle and ±50 ppm accuracy.

  • Page 12: Design Example: Cs8900A Interface To Cirrus Logic Cl-Ps7111

    Inverter on the IRQ line. Design Example: CS8900A Interface to Only 16 bit accesses Cirrus Logic CL-PS7211 Summary This design is similar to the MC68302 except that The CS8900A can be interfaced to most non-ISA only the I/O mode data access is supported.
  • Page 13 DMARQ0 nCS2 nCS2 SBHE DMARQ1 DMARQ2 CS8900_RST RESET SLEEP DMACK0 TESTSEL DMACK2 ELCS DMACK3 XTLI CSOUT XTLO CS8900A 20MHz U30A nURESET CS8900_RST nURESET 74LVX04 100nF 100nF 100nF 100nF 100nF 100nF 100nF Figure 4. CS8900A Interface to Cirrus Logic CL-PS7211 AN83REV3...
  • Page 14 AN83 3.3V 3.3V SH3 A1 SH3 A2 SH3 A3 RDX- RXD+ SA10 SA11 SA12 TXD- SA13 SA14 RXD- SA15 RXD+ 560pF SA16 TXD- TXD+ SA17 TXD+ SA18 3.3V SA19 BSTATUS/HC1 LINKLED/HC0 LANLED CSOUT XTAL1 20MHz XTAL2 SD10 SD11 SD12 SD13 SD14 SD15 CS8900A-CQ3...

  • Page 15: Ethernet Hardware Design For Embedded Systems And Motherboards

    AN83 ETHERNET HARDWARE DESIGN FOR the CS8900A to interface with variety of micro- EMBEDDED SYSTEMS AND processors directly or with the help of simple pro- MOTHERBOARDS grammable logic like a PAL or a GAL. This section describes the hardware design of a This reference design uses the ISA adapter card four-layer, 10BASE-T solution intended for use on form factor.
  • Page 16 AN83 Figure 6. Placement of Components, Top Side AN83REV3...
  • Page 17 AN83 Figure 7. Placement of Components, Solder Side AN83REV3...

  • Page 18: Leds

    AN83 PROM is not necessary for the CS8900A, and the tion transformer at location T1. This isolation CS8900A will respond to IO addresses 0300h transformer has a 1:1 ratio between the primary and through 030Fh after a reset. the secondary windings on the receive side. It has a 1:√2 (1:1.414) ratio between the primary and the Please refer to the CS8900A data sheet for informa- secondary windings for the transmit lines for 5V...
  • Page 19 AN83 0.1 µ F EE_CLK 1K_EEPROM_S 4.99k, 1% XTAL XTL1 20.0 MHz XTL2 EECS ISA0 EEDATAOUT SA00 ISA1 SA01 ISA2 SA02 LED0/HC0 ISA3 SA03 ISA4 BSTATUS / HC1 SA04 LED2 ISA5 SA05 ISA6 SA06 ISA7 SA07 ISA8 SA08 ISA9 SA09 ISA10 SA10 ISA11...

  • Page 20: Component Placement And Signal Routing

    AN83 10BT_RD- (1-3) (16-14) 1:1 10BT_RD+ 10BT_TD- (6-8) (11-9) 1:1.414 68 pF 24.3 10BT_TD+ 24.3 10 BaseT Transformer Do Not Do Not Populate .1 µF Populate .1 µF .1 µF 2KV .1 µF 2KV Figure 10. 10BASE-T Schematic 5V Component Placement and Signal Routing Please refer to “Layout Considerations for the CS8900A”...

  • Page 21: Low Cost Ethernet Combo Card Reference Design: Crd8900

    AN83 LOW COST ETHERNET COMBO CARD External Decode Logic REFERENCE DESIGN: CRD8900 The CS8900A can be accessed in both I/O and This section describes the hardware design of a low- memory modes. The CS8900A internally decodes cost, two-layer, full-featured Ethernet solution in- the SA[0:19] address lines for the lower 1 M of tended for use in PC ISA-bus.
  • Page 22 AN83 Figure 12. Placement of Components AN83REV3...
  • Page 23 AN83 0.1µF EE_CLK ELCS 1K_EEPROM_S 4.99k BSTATUS / HC1 XTAL 20.0 MHz XTL1 XTL2 LED_T EECS ISA0 SA00 EEDATAOUT ISA1 SA01 ISA2 SA02 LED0/HC0 99 LED_B ISA3 SA03 BSTATUS / HC1 ISA4 SA04 LED2 ISA5 SA05 ISA6 SA06 ISA7 SA07 ISA8 SA08 ISA9...
  • Page 24 AN83 TANT TANT TANT 22 µ F 22 µ F 22 µ F Figure 14. Power Supply Decoupling Schematic PROM_CS 0.1 µ F 0.1 µ F 4.7k SA00 SA01 SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SA10 SA11 SA12 SA13 SA14 27C256...
  • Page 25 AN83 +12V VP_+12V 0.1 µ F CON_AUI15PSUBO 39.2 39.2 CI_B CI_A DO_A DO_B DI_B DI_A 39.2 Ω R9 39.2 AUI_XFR_S 0.1 µ F 0.1 µ F Figure 16. AUI Schematic +12IN1 ISOLATED_GND SOUT+ +12V +12IN2 SOUT- 0.1 µ F 0.1 µ F BSTATUS/HCI -9_V 0.1 µ...

  • Page 26: Leds

    AN83 loaded at the Boot PROM base address register in- up when the CS8900A has the link pulse. The bot- dicates the starting location in host memory where tom LED lights up when the CS8900A transmits or the Boot PROM is mapped. The Boot PROM ad- receives a packet or senses a collision.

  • Page 27: 10Base-2 Interface

    AN83 10BASE-2 Interface ment for an explanation and information about placement of components on the board. A 10BASE-2 transceiver IC, the 83C92C, is used to generate a 10BASE-2 interface for the reference Bill of Material design. Please refer to Figure 17 for details about Table 3 contains a list of components that are typi- the components and connection.
  • Page 28 AN83 Figure 19. CRD8900 Top-Side Routing AN83REV3...
  • Page 29 AN83 Figure 20. CRD8900 Bottom Side Routing AN83REV3...
  • Page 30 AN83 Item Reference # Description Quantity Vendor Part Number Base Configuration: I/O Mode with 10BASE-T Interface C5, C7, C8, Capacitor, 0.1 µF, SMT0805, X7R C11..13, C16, C17, C22, C23, C27 C1, C10, C19 Capacitor, 22 µF, SMT7343 Resistor, 4.99K, 1%, SMT0805 R18, R19 Resistor, 681, 5%, 1/8W, SMT0805 Crystal, 20.000MHz,18 pF...

  • Page 31: Memory Mode

    AN83 Memory Mode Extended Memory Mode In the memory mode, there are two options where The CS8900A can also be mapped in to the extend- the CS8900A can be placed in the ISA memory ad- ed memory of a Personal Computer (PC) system. dress map, lower memory (below 1 Meg) or ex- This provides flexibility and more options when tended memory (above 1 Meg).
  • Page 32 AN83 CS8900 Figure 22. Typical CS8900A Ethernet Connection face is used to generate the serial data stream on CS8900A samples ELCS pin and if it is not EEDataOut pin (serial data out) with the EESK (se- "LOW", it realizes presence of external address de- rial clock).
  • Page 33 AN83 Figure 23 shows a simple PALASMTM program for the 16R4 PAL that is used in the design shown in Figure 21. ;PALASM Design Description ;---------------------------------- Declaration Segment ------------ TITLE High address decoder PATTERN REVISION AUTHOR Deva Bodas COMPANY Crystal Semiconductor DATE 04/01/1994 CHIP...
  • Page 34 AN83 Q20 := (Q20 * CS_EL_b) + (/CS_EL_b * SDATA) Q21 := (Q21 * CS_EL_b) + (/CS_EL_b * Q20) Q22 := (Q22 * CS_EL_b) + (/CS_EL_b * Q21) Q23 := (Q23 * CS_EL_b) + (/CS_EL_b * Q22) ; Decode logic EQUALL = (Q20:*:LA20) * (Q21:*:LA21) ;...

  • Page 35: Layout Considerations For The Cs8900A

    AN83 Layout Considerations for the CS8900A nect the capacitor to the pads of the power pins by short, wide traces, the other end of these traces The CS8900A is a mixed signal device having dig- should be connected to VCC and GND planes. Fig- ital and analog circuits for an Ethernet communica- ure 19 and Figure 20 illustrate ground and power tion.
  • Page 36 AN83 Figure 24. General placement on an ISA adapter card AN83REV3...
  • Page 37 AN83 Figure 25. Placement of Components, Top Side AN83REV3...
  • Page 38 AN83 Figure 26. Placement of Components, Solder Side AN83REV3...
  • Page 39 AN83 Figure 27. Component (top) side of four-layer board Figure 2.4.6. Component (top) side of four-layer board AN83REV3...
  • Page 40 AN83 Figure 28. +5V Plane of four-layer board Figure 2.4.7. +5V Plane of four-layer board AN83REV3...
  • Page 41 AN83 Figure 29. Ground Plane of four-layer board Figure 2.4.8. Ground Plane of four-layer board AN83REV3...
  • Page 42 AN83 Figure 30. Solder side (bottom) of four-layer board Figure 2.4.9. Solder side (bottom) of four-layer board AN83REV3...
  • Page 43 AN83 Figure 31. Placement of Decoupling Capacitor (Bottom side, under CS8900A) Figure 32. Routing of Decoupling Capacitor (Top side, component side) The 20.000 MHz crystal traces should be short, ferential transmit signals and two differential re- have no via, and run on the component side. ceive signals.

  • Page 44: Recommended Magnetics For The Cs8900A

    AN83 mit signal traces should be at least 100 mil. This will provide a good impedance matching for the transmit and receive circuitry inside the CS8900A. A ground trace should be run parallel to the trans- mit traces. Also, a ground plane should run under- neath the transmit and receive traces on the solder side of a two layered PCB.

  • Page 45: Jumperless Design

    AN83 able in a 16 pin DIP or 16 pin SOIC package. See tables 4 and 5 for recommended part numbers. JUMPERLESS DESIGN Using the CS8900A, both add-in adapters and motherboard solutions can be implemented without hardware jumpers or switches. The CS8900A and media access control (MAC) device drivers obtain configuration information directly from nonvola- tile memory.
  • Page 46 AN83 Vendor name Description Through-hole Surface-mount Halo Electronics Isolation transformer, 100 µH TD01-1006K TG01-1006N Pulse Engineering Isolation transformer, 100 µH PE-64503 PE-65728 Valor Electronics Isolation transformer, 100 µH LT6033 ST7033 Table 4. Partial List of Recommended AUI Transformers Vendor name Description Through-hole Surface-mount...

  • Page 47: Driver Configuration Information

    AN83 Sheet for additional information on the operation of tional configuration information can be stored in the EEPROM. the EEPROM and accessed by the MAC driver. Typically, this additional configuration informa- Addr Word Description tion includes the unique IEEE physical address for A110h Sequential EEPROM, 16 bytes follow the adapter.
  • Page 48 AN83 Addr. Description Bit(s) Function Transmission Control HDX/FDX 0 = Half-Duplex, 1 = Full-Duplex Reserved 14-7 Reserved for future use, set to 0 Ignore Missing Media 0 = Media required for driver to load, 1 = media not required Reserved Reserved for future use, set to 0 Adapter Configuration Ext.

  • Page 49: Ieee Physical Address

    AN83 IEEE Physical Address The format of the 48-bit IEEE physical address as expected by the MAC driver is illustrated by the follow- ing example. (Must be initialized by OEM before shipping adapter.) Example physical address: 000102030405h Addr Word Description 0100h 2 MSB of address (byte reversed) 0302h Middle 2 bytes (byte reversed) 0504h 2 LSB of address (byte reversed)

  • Page 50: Packetpage Memory Base

    AN83 PacketPage Memory Base Bits 15-4 12 MSB of Memory Base Address - The twelve most significant bits of the 24-bit address locating the base of the CS8900A’s PacketPage memory. The lower twelve bits are as- sumed to be 0. Default is 0. Bits 3-0 Reserved (set to 0) Boot PROM Memory Base...

  • Page 51: Adapter Configuration Word

    AN83 Adapter Configuration Word Bits 15-13 Reserved (set to 0) Bits 12-11 Optimization Flags Used to specify the platform’s OS configuration to the driver. Each driver configures the CS8900A for optimum performance based on the platform’s OS and driver architecture (NDIS 2X, ODI, NDIS 3X, etc.).

  • Page 52: Manufacturing Date

    AN83 Manufacturing Date This word is the adapter’s manufacture date encoded in 16 bits, YR-MO-DY format. (Must be initialized by OEM before shipping adapter.) Bits 15-9 Two Least-significant Digits of Year Seven bits for a range of 00 to 99 decimal. A roll-over to 00 will be interpreted as the year 2000.

  • Page 53: Serial Number

    AN83 Serial Number The two serial number words make up the unique 32-bit OEM serial number for the adapter. Low Word Bits 7-0 bits[7-0] of 32-bit serial number Bits 15-8 bits[15-8] of 32-bit serial number High Word Bits 7-0 bits[31-24] of 32-bit serial number Bits 15-8 bits[23-16] of 32-bit serial number Serial ID Checksum...

  • Page 54: Maintaining Eeprom Information

    AN83 Maintaining EEPROM Information 4) The header must be located on a 512-byte boundary in the BIOS space between C0000h The contents of the EEPROM may either be pre- and FFC00h. programmed in a stand-alone EEPROM program- 5) The data structure must employ the same for- mer or programmed after installation through the mat as defined for EEPROM in Table 8.

  • Page 55: Obtaining Ieee Addresses

    This 24 bit address is known as Organization- IEEE Physical Address obtained from an allotment ally Unique Identifier (OUI). The remaining 24 assigned to Cirrus Logic by the IEEE. bits of the address are assigned by the manufactur- er. For further information and an application for...

  • Page 56: Device Drivers And Setup/Installation Software

    AN83 DEVICE DRIVERS AND internal testing and evaluation purposes. This ob- SETUP/INSTALLATION SOFTWARE ject code may not be distributed without first sign- ing a LICENSE FOR DISTRIBUTION OF This chapter discusses the software provided by EXECUTABLE SOFTWARE, which may be ob- Cirrus for use with the CS8900A.

  • Page 57: Contacting Customer Support At Cirrus

    Cirrus Web Site stallation Utility. Cirrus also offers free updates to the of the network CONTACTING CUSTOMER SUPPORT driver software using the Cirrus website: AT CIRRUS http://ww.cirrus.com. Cirrus Logic is committed to providing the indus- try’s most easily implemented Ethernet solution. AN83REV3...

Table of Contents