Pwmout Delay Register (Address 33H); Differential Signal Delay (Diff_Dly[2:0]); Channel Delay Settings (Chnl_Dly[4:0]); Table 14. Pwm Minimum Pulse Width Settings - Cirrus Logic CS44600 Manual

Power Control (address 02h)" on page 51
will be ignored.
7.31

PWMOUT Delay Register (address 33h)

7 6
DIFF_DLY2 DIFF_DLY1

7.31.1 Differential Signal Delay (DIFF_DLY[2:0])

Default = 000
Function:
The Differential Signal Delay bits allow delay adjustment between each channel's differential signals,
PWMOUTxx+ and PWMOUTxx-. This set of bits control the delay between PWMOUTxx+ and PW-
MOUTxx- across all active channels. The value of this register determines the amount of delay inserted
in the output path. The effective delay is calculated by multiplying the register value by the period of the
PWM_MCLK. This parameter can only be changed when all modulators and associated logic are in the
power-down state by setting the PDN bit in the register
02h)" on page 51
7.31.2

Channel Delay Settings (CHNL_DLY[4:0])

Default = 00000
Function:
The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PW-
MOUTAx+/PWMOUTAx- from the associated PWMOUTBx+/PWMOUTBx-. The value of this register de-
termines the amount of delay inserted in the output path. The effective delay is calculated by multiplying
the register value by the period of the PWM_MCLK. This parameter can only be changed when all mod-
ulators and associated logic are in the power-down state by setting the PDN bit in the register
figuration and Power Control (address 02h)" on page 51
PDN is not set will be ignored.
68
Binary Code
MIN_PULSE[4:0]
00000
00110
10100
11111

Table 14. PWM Minimum Pulse Width Settings

5 4
DIFF_DLY0 CHNL_DLY4
to a 1b. Attempts to write this register while the PDN is not set will be ignored.
Binary Code
000
001
100
111

Table 15. Differential Signal Delay Settings

Binary Code Delay Setting(multiply by PWM_MCLK period)
00000
00110
11000
11111

Table 16. Channel Delay Settings

to a 1b. Attempts to write this register while the PDN is not set
Minimum Pulse
Setting (multiply by
PWM_MCLK period)
0 - no minimum
6
20
31
3
CHNL_DLY3 CHNL_DLY2
"Clock Configuration and Power Control (address
Delay Setting (multiply by
PWM_MCLK period)
0 - no delay
1
4
7
to a 1b. Attempts to write this register while the
0 - no delay
6
24
31
CS44600
2 1
CHNL_DLY1 CHNL_DLY0
"Clock Con-
0
DS633F1