Figure 19.Right-Justified Serial Audio Formats; Figure 20.One Line Mode #1 Serial Audio Format - Cirrus Logic CS44600 Manual

4.4.1.3 Right-Justified Data Format
In the right-justified format, data is received most significant bit first and with the least significant bit pre-
sented on the last DAI_SCLK before the DAI_LRCK transition and is valid on the rising edge of
DAI_SCLK. For the right-justified format, the left channel data is presented when DAI_LRCK is high and
the right channel data is presented when DAI_LRCK is low. Either 16 bits per sample or 24 bits per sam-
ple are supported.
DAI_LRCK
DAI_SCLK
DAI_SDINx
4.4.1.4 One Line Mode #1
In One Line mode #1 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 128Fs
rate. DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sam-
pled as valid on the same clock edge as the most significant bit of the first data sample and must be held
high for 64 DAI_SCLK periods. Each time slot is 20 bits wide, with the valid data sample left-justified within
the time slot. Valid data lengths are 16, 18, or 20 bits. Valid samples rates for this mode are 32 kHz to
96 kHz.
DAI_LRCK
DAI_SCLK
MSB
DAI_SDIN1
PWMOUTA1
20 clks
28
Left Channel
15 14 13 12 11 10 9 8 7 6 5
Right-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample SCLK Rate(s)
16 32, 48, 64, 128, 256 Fs
24 48, 64, 128, 256 Fs
Figure 19. Right-Justified Serial Audio Formats
64 clks
Left Channels
LSB MSB LSB MSB
PWMOUTA2 PWMOUTA3
20 clks 20 clks
Figure 20. One Line Mode #1 Serial Audio Format
4 3 2 1 0 15 14 13 12 11 10
LSB MSB LSB MSB
PWMOUTB1 PWMOUTB2
20 clks
CS44600
Right Channel
9 8 7 6 5 4 3
64 clks
Right Channels
LSB MSB LSB
PWMOUTB3
20 clks 20 clks
2 1 0
MSB
DS633F1