1. Manuals
  2. Brands
  3. Cirrus Logic Manuals
  4. Controller
  5. Crystal LAN CS8900A
  6. Product data sheet

Cirrus Logic Crystal LAN CS8900A Series Product Data Sheet

Hide thumbs Also See for Crystal LAN CS8900A Series:
Table of Contents

Advertisement

Quick Links

Download this manual See also: Reference Manual
FEATURES
Single-Chip IEEE 802.3 Ethernet Controller with
Direct ISA-Bus Interface
Maximum Current Consumption = 55 mA (5V Supply)
3 V Operation
Industrial Temperature Range
Comprehensive Suite of Software Drivers Available
Efficient PacketPage™ Architecture Operates in
I/O and Memory Space, and as DMA Slave
Full Duplex Operation
On-Chip RAM Buffers Transmit and Receive Frames
10BASE-T Port with Analog Filters, Provides:
— Automatic Polarity Detection and Correction
AUI Port for 10BASE2, 10BASE5 and 10BASE-F
Programmable Transmit Features:
— Automatic Re-transmission on Collision
— Automatic Padding and CRC Generation
Programmable Receive Features:
— Stream Transfer™ for Reduced CPU Overhead
— Auto-Switch Between DMA and On-Chip Memory
— Early Interrupts for Frame Pre-Processing
— Automatic Rejection of Erroneous Packets
EEPROM Support for Jumperless Configuration
Boot PROM Support for Diskless Systems
Boundary Scan and Loopback Test
LED Drivers for Link Status and LAN Activity
Standby and Suspend Sleep Modes
I
S
A
DS271PP3
EEPROM
CS8900A ISA Ethernet Controller
LED
Control
EEPROM
RAM
Control
ISA
Bus
Logic
802.3
Memory
MAC
Boundary
Manager
Engine
Scan
Test Logic
CIRRUS LOGIC PRODUCT DATA SHEET
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
&U\VWDO /$1 ™ ISA Ethernet
Controller
DESCRIPTION
The CS8900A is a low-cost Ethernet LAN Controller op-
timized for Industry Standard Architecture (ISA)
Personal Computers. Its highly-integrated design elimi-
nates the need for costly external components required
by other Ethernet controllers. The CS8900A includes
on-chip RAM, 10BASE-T transmit and receive filters,
and a direct ISA-Bus interface with 24 mA Drivers.
In addition to high integration, the CS8900A offers a
broad range of performance features and configuration-
options.
Its
unique
automatically adapts to changing network traffic pat-
terns and available system resources. The result is
increased system efficiency.
The CS8900A is available in a 100-pin TQFP package-
ideally suited for small form-factor, cost-sensitive
Ethernet applications. With the CS8900A, system engi-
neers can design a complete Ethernet circuit that
occupies less than 1.5 square inches (10 sq. cm) of
board space.
ORDERING INFORMATION
CS8900A-CQ
CS8900A-IQ
CS8900A-CQ3 0° to 70° C
CS8900A-IQ3
CRD8900A-1
20 MHz
XTAL
Clock
10BASE-T
RX Filters &
Receiver
10BASE-T
TX Filters &
Encoder/
Transmitter
Decoder
&
PLL
AUI
Transmitter
AUI
Collision
Power
AUI
Manager
Receiver
CS8900A
Product Data Sheet
PacketPage
architecture
0° to 70° C
5V
TQFP-100
-40° to 85° C 5V
TQFP-100
3.3V
TQFP-100
-40° to 85° C 3.3V
TQFP-100
Evaluation Kit
RJ-45 10BASE-T
Attachment
Unit
Interface
(AUI)
MAR '99

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Crystal LAN CS8900A Series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Cirrus Logic Crystal LAN CS8900A Series

Summary of Contents for Cirrus Logic Crystal LAN CS8900A Series

  • Page 1 TX Filters & Encoder/ Transmitter Decoder & Logic Transmitter Attachment Unit 802.3 Memory Interface Collision Boundary Manager (AUI) Engine Power Scan Manager Test Logic Receiver CIRRUS LOGIC PRODUCT DATA SHEET Copyright © Cirrus Logic, Inc. 1999 DS271PP3 MAR ‘99 (All Rights Reserved)

  • Page 2: Table Of Contents

    3.4.3.5 Determining Number of Bytes in the Reset Configuration Block ........22 3.4.4 Groups of Configuration Data ....................22 3.4.4.1 Group Header........................23 3.4.5 Reset Configuration Block Checksum ..................23 3.4.6 EEPROM Example ........................23 3.4.7 EEPROM Read-out ........................23 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 3 3.9.5.7 Backoff ..........................33 3.9.5.8 Standard Backoff......................33 3.9.5.9 Modified Backoff....................... 33 3.9.5.10 SQE Test........................33 3.10 Encoder/Decoder (ENDEC) ......................34 3.10.1 Encoder ........................... 34 3.10.2 Carrier Detection ........................34 3.10.3 Clock and Data Recovery ......................34 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 4 4.4.3.4 Accept Bits ........................48 4.4.4 Status and Control Register Summary ..................49 4.4.5 Register 0: Interrupt Status Queue ..................52 4.4.6 Register 3: Receiver Configuration ..................53 4.4.7 Register 4: Receiver Event ...................... 54 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 5 5.1 Managing Interrupts and Servicing the Interrupt Status Queue ............79 5.2 Basic Receive Operation........................79 5.2.0.1 Overview .......................... 79 5.2.1 Terminology: Packet, Frame, and Transfer ................81 5.2.1.1 Packet ..........................81 5.2.1.2 Frame..........................81 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 6 5.6.4 Keeping StreamTransfer Mode Active ..................96 5.6.5 Example of StreamTransfer ....................... 98 5.6.6 Receive DMA Summary......................98 5.7 Transmit Operation..........................99 5.7.1 Overview ............................ 99 5.7.2 Transmit Configuration....................... 99 5.7.2.1 Configuring the Physical Interface..................99 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 7 9.0 GLOSSARY OF TERMS......................... 123 9.1 Acronyms ............................123 9.2 Definitions ............................124 9.3 Acronyms Specific to the CS8900A ....................125 9.4 Terms Specific to the CS8900A ......................125 9.5 Suffixes Specific to the CS8900A..................... 126 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 8: Introduction

    1.5 square inches of PCB area (Figure 1). In addi- eration and detection, and CRC generation and test. tion, the CS8900A’s power-saving features and Programmable MAC features include automatic re- CMOS design make it a perfect fit for power-sensi- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 9: Ethernet Adapter Cards

    (Figure 2). The CS8900A’s wide range of configu- tional LEDs, or as programmable outputs. ration options and performance features allow en- RJ-45 20 MHz EEPROM XTAL ’245 Attachment CS8900A Unit Interface Boot PROM (AUI) Figure 2. Full-Featured ISA Adapter Solution CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 10: Key Features And Benefits

    CPU/ISA-bus configuration. When compared to required to produce new Ethernet products. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 11 680 Ω IRQ10 INTRQ0 LINKLED IRQ11 INTRQ1 IRQ12 INTRQ2 CSOUT IRQ5 INTRQ3 74LS245 Boot-PROM 27C256 DRQ5 DMARQ0 DACK5 DMACK0 DRQ6 DMARQ1 DACK6 DMACK1 DRQ7 DMARQ2 PD[0:7] DACK7 DMACK2 SA[0:14] SD[0:7] Figure 3. Typical Connection Diagram CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 12: Pin Description

    CS8900A DVSS1 DVDD1 DVSS1A DMARQ2 DMACK2 IOCHRDY 100-pin DMARQ1 DMACK1 TQFP DMARQ0 DMACK0 SA19 CSOUT SA18 SD15 Top View SA17 SD14 DVSS3A SD13 DVDD3 SD12 DVSS3 DVDD2 SA16 DVSS2 SA15 SD11 SA14 SD10 SA13 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 13 IOW - I/O Write, Input PIN 62. When IOW is low and a valid address is detected, the CS8900A writes the data on the System Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 14 EEPROM and Boot PROM Interface EESK - EEPROM Serial Clock, PIN 4. Serial clock used to clock data into or out of the EEPROM. EECS - EEPROM Chip Select, PIN 3. Active-high output used to select the EEPROM. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 15 A 20 MHz crystal should be connected across these pins. If a crystal is not used, a 20 MHz signal should be connected to XTAL1 and XTAL2 should be left open. (See Section 7.3 on page 111 and Section 7.7 on page 121.) CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 16 Provides 5 V ± 5% power to the analog circuits of the CS8900A. AVSS[0:4] - Analog Ground, Ground PINS 1, 89, 86, 94, 96. Provide ground reference (0 V) to the analog circuits of the CS8900A. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 17: Functional Description

    The Section 5.2 on page 79 through Section 5.6 on In the second phase of transmission, the CS8900A page 96 provide a detailed description of packet re- converts the frame into an Ethernet packet then ception. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 18: Isa Bus Interface

    DMA. If the DMABurst bit (reg- ister 17, BusCTL, Bit B) is clear, the pin goes low For additional information about I/O Mode, see after the DMA operation is complete. If the Section 4.10 on page 76. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 19: Reset And Initialization

    IObase+0Ah. The 3000h value can be used as a level greater than approximately 2.5 V and the part of the CS8900A signature when the system crystal oscillator has stabilized. scans for the CS8900A. See Section 4.10 on page 76. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 20: Initialization

    * I/O base address is unaffected by Software Suspend mode. Table 3. efault Configuration EEPROM Type Size (16-bit words) ‘C46 (non-sequential) ‘CS46 (sequential) ‘C56 (non-sequential) ‘CS56 (sequential) ‘C66 (non-sequential) ‘CS66 (sequential) Table 4. Supported EEPROM Types CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 21: Configurations With Eeprom

    24 for more information on accessing the EE- ommends that the high byte of the first word be PROM). Address space 80h to AFh is reserved. programmed with 00h in order to ensure that the CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 22: Determining Number Of Bytes In The Reset Configuration Block

    Configuration data are arranged as groups of calculating the Link Byte value. words. Each group contains one or more words of data that are to be loaded into PacketPage registers. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 23: Group Header

    Group header. The CS8900A determines the size of the EEPROM by checking the sense of EEDI on the tenth rising edge of EESK. If EEDI is low, the EEPROM is a CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 24: Loading Configuration Data

    When set, the ELCS pin is used to select the external LA decode circuit. [9:8] OP1, OP0 Opcode: Indicates what command is being executed (see next section). [7:0] AD7 to AD0 EEPROM Address: Address of EEPROM word being accessed. Figure 5. EEPROM Command Register Format CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 25: Enabling Access To The Eeprom

    3) Issue a Write command. must be loaded into the Boot PROM Base Address 4) Issue an Erase/Write Disable command. register (PacketPage base + 0030h) and the Boot PROM Address Mask must be loaded into the CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 26: Low-Power Modes

    (Register 15, SelfCTL, bit 9) while the HWStand- is set indicating that initialization is complete, and byE bit (Register 15, SelfCTL, bit A) is clear. To the SIBUSY bit in the same register is cleared (in- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 27: Software Suspend

    High Not in low-power mode High SW Suspend mode SW Suspend mode Not in low-power mode Notes: 1. Both HW and HW Suspend take precedence over SW Suspend. Table 8. Low-Power Mode Operation CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 28: Led Outputs

    ISA bus. To configure this pin for and reception, including: collision detection, pre- CS8900A control, the HC1E bit (Register 15, Self- amble generation and detection, and CRC genera- CTL, Bit D) must be clear. When controlled by the CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 29: Frame Encapsulation And Decapsulation

    SFD = Start of Frame Delimiter LLC = Logical Link Control DA = Destination Address FCS = Frame Check Sequence (also SA = Source Address called Cyclic Redundancy Check, or CRC) Figure 9. Ethernet Frame Format CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 30: Transmit Error Detection And Handling

    The MAC then forces a bad CRC and termi- by setting the Out-of-window bit (Register 8, Tx- nates the transmission. If the TxUnderruniE bit Event, Bit 9). The MAC then forces a bad CRC and terminates the transmission. If the Out-of-window- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 31: Receive Error Detection And Handling

    The Ethernet network topology is a single shared 6.4 µs of the IPG timer, the IPG timer is allowed to medium with several attached stations. The Ether- time out (even if network activity is detected during CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 32: Simple Deferral

    Backoff. Frame In either case, if the Onecoll bit (Register 9, TxC- Figure 10. Two-Part Deferral MD, Bit 9) is clear, the MAC will attempt to trans- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 33: Late Collisions

    SQE Test sig- Frame CI+/CI- pair following each transmission. The SQE Test is a 10 MHz signal Figure 11. Simple Deferral lasting 5 to 15 bit times and starting within 0.6 to CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 34: Encoder/Decoder (Endec)

    MAC for further processing. ENDEC RXSQL Carrier Carrier Sense Detector 10BASE-T Transceiver RX CLK Decoder & PLL RX NRZ AUISQL TXCLK AUIRX Encoder TX NRZ AUITX Port Select AUICol Collision Clock Figure 12. ENDEC CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 35: Interface Selection

    3 dB cutoff frequency of the filters is 16 MHz, by the 10BASE-T receiver. If valid packets and and the nominal attenuation at 30 MHz (3rd har- link pulses are not detected, the CS8900A selects monic) is -27 dB. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 36: Transmitter

    RXD+/RXD- pair. In- packet itself is ignored), or two link pulses separat- coming signals passing through the receive filter Time Link Link Pulse Pulse Packet Packet Less Than 16ms 16ms 16ms Figure 14. Link Pulse Transmission CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 37: Receive Polarity Detection And Correction

    When a collision is present, presence indicates that the transmit signal is getting the Collision Detection circuit informs the MAC by through to the transceiver. If the Carrier Sense sig- nal remains deasserted throughout the transmis- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 38: Aui Receiver

    The AUI collision circuit is a differential pair re- crystal are described in Section 7.7 on page 121. ceiver that detects the presence of collision signals on the CI+/CI- pins. The collision signal is generat- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 39: Packetpage Architecture

    0400h Receive Frame Location formance. As a result of this dynamic allocation, 0A00h Transmit Frame Location only one receive frame (starting at PacketPage base + 0400h) and one transmit frame (starting at Pack- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 40: Packetpage Memory Map

    Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. Table 12. PacketPage Memory Address Map CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 41 Notes: 1. All registers are accessed as words only. 2. Read operation from the reserved location provides undefined data. Writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. Table 12. PacketPage Memory Address Map (continued) CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 42: Bus Interface Registers

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0011 0000 0000 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 43: Interrupt Number

    DMRQ pins to high-impedance. If a EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX XX11 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 44: Dma Start Of Frame

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 45: Boot Prom Base Address

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 46: Eeprom Command

    This register contains the count of the total number bytes received in the the current received frame. This count con- tinuously increments as more bytes in this frame are received. See Section 5.2.9 on page 87. Reset value is: XXXX XXXX XXXX XXXX CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 47: Status And Control Registers

    PacketPage base + 0108h, is within the block of Configuration/Control Registers and is 16-bit Register Word Bit Number Internal Address (bits 0 - 5) 1 = Control/Configuration 0 = Status/Event 10 Register Bits Figure 16. Status and Control Register Format CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 48: Act-Once Bits

    Interrupt Enable bits end with the suffix iE and are corresponding Interrupt Enable (iE) bits. An Ac- located in three Configuration registers: RxCFG cept bit and an Interrupt Enable bit are independent (Register 3), TxCFG (Register 7), and BufCFG CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 49: Status And Control Register Summary

    ExtradataiE ExtradataA RuntiE RuntA CRCerroriE CRCerrorA RxOKiE RxOKA If one of the above Interrupt Enable bits is set and the corresponding Accept bit is clear, the CS8900A generates an interrupt when the associated receive CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 50 Memo- UseSA DMAex- Reset BusCTL e IRQ size RDYE Burst tend RxDMA (0116) Disable AUIloop ENDEC Disable TestCTL Backoff loop (0118) Reserved (register contents undefined) 1B -1F Table 15. Status and Control Register Descriptions CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 51 Mpresent Active (0136h) Rdy4Tx TxBid BusST (0138h) Reserved (register contents undefined) 10-bit AUI Time Domain Reflectometer (TDR) counter, cleared when read (013Ch) Reserved (register contents undefined) Table 15. Status and Control Register Descriptions (continued) CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 52: Register 0: Interrupt Status Queue

    The lower six bits describe which register (4, 8, C, 10 or 12) is contained in the ISQ. RegContent The upper ten bits contain the register data contents. Reset value is: 0000 0000 0000 0000 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 53: Register 3: Receiver Configuration

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0000 0011 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 54: Register 4: Receiver Event

    4. RxStatus register (PacketPage base + 0400h) is the same as the RxEvent register except RxStatus is not cleared when RxEvent is read. See Section 5.2 on page 79. The value in the RxEvent register is undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 55: Register 5: Receiver Control

    Notes: 5. Typically, when bits CRCerrorA, RuntA and ExtradataA are cleared (meaning bad frames are being discarded), then the corresponding bits CRCerroriE, RuntiE and ExtradataiE should be set in register 3 (Receiver Configuration register) to allow the device driver to keep track of discarded frames. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 56: Register 7: Transmit Configuration

    Reset value is: 0000 0000 0000 0111 Notes: Bit 8 (TxOKiE) and Bit B (AnycolliE) are interrupts for normal transmit operation. Bits 6, 7, 9, A, and FNotes: are interrupts for abnormal transmit operation. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 57: Register 8: Transmitter Event

    1.In any event register, like TxEvent, all bits are cleared upon readout. The host is responsible for processing all event bits. 2.TxOK (Bit 8) and the Number-of-Tx-Collisions (Bits E-B) are used in normal packet transmission.All other bits (6, 7, 9, A, and F) give the status of abnormal transmit operation. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 58: Register 9: Transmit Command Status

    EEPROM. See Section 3.3 on page 19. Regster value is: 0000 0000 0000 1001 Notes: The CS8900A does not transmit a frame if TxLength < 3 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 59: Register B: Buffer Configuration

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state after reset. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0000 1011 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 60: Register C: Buffer Event

    B, BufCFG, Bit F) is set, there is an interrupt. 0000 0000 0000 1100 Reset value is: Notes: With any event register, like BufEvent, all bits are cleared upon readout. The host is responsible for processing all event bits. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 61: Register 10: Receiver Miss Counter

    Miss Counter. When reading this register, these bits will be 010000, where the LSB corre- sponds to Bit 0. MissCount The upper ten bits contain the number of missed frames. Register’s value is: 0000 0000 0001 0000 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 62: Register 10: Transmit Collision Counter

    Collision Counter. When reading this register, these bits will be 010010, where the LSB corre- sponds to Bit 0. ColCount The upper ten bits contain the number of collisions. Reset value is: 0000 0000 0001 0010 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 63: Register 13: Line Control

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 0011 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 64: Register 14: Line Status

    CRS remains asserted until the end of frame (EOF). At EOF, CRS goes inactive in about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered data. 0000 0000 0001 0100 Reset value is: CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 65: Register 15: Self Control

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 0101 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 66: Register 16: Self Status

    (Bit 9) and EEPROMOK bit (Bit A) are both set. If clear, the EEPROM size is either 128 words (’C56 or ’CS56) or 256 words (C66 or ’CS66). If set, the EEPROM size is 64 words (’C46 or ’CS46). Reset value is: 0000 0000 0001 0110 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 67: Register 17: Bus Control

    After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 0111 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 68: Register 18: Bus Status

    Rdy4TxNOW. The host can poll the CS8900A and check Rdy4TxNOW to determine if the CS8900A is ready for transmit. (See Section 5.7 on page 99 for a description of the transmit bid process.) Reset value is: 0000 0000 0001 1000 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 69: Register 19: Test Control

    At reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 1001 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 70: Register 1C: Aui Time Domain Reflectometer

    The upper ten bits contains the number of 10 MHz clock periods between the beginning of transmission on the AUI to when a collision or Loss-of-Carrier error occurs. Reset value is: 0000 0000 0001 1100 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 71: Initiate Transmit Registers

    TxPadDis and InhibitCRC bits in the TxCMD register. See Table 35, and Section 5.7 on page 99. TxLength must be >3 and < 1519. Since this register is write-only, it’s initial state after reset is undefined. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 72: Address Filter Registers

    19. If the CS8900A is not able to load the IA from the EEPROM, then after a reset this register is undefined, and the driver must write an address to this register. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 73: Receive And Transmit Frame Locations

    CRC, and the CRC is not present in the lowed by a word access. receive buffer. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 74: Transferring Odd-Byte-Aligned Data

    CS8900A for Memory Mode operation. One meth- CS8900A comes out of reset, its default configura- od allows the CS8900A's internal memory to be tion is I/O Mode. Once Memory Mode is selected, mapped anywhere within the host system's 24-bit CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 75: Basic Memory Mode Transmit

    CHIPSEL pin must be tied low; Memory Mode receive operations occur in the fol- • the ISA-bus SMEMR signal must be connected lowing order (interrupts used to signal the presence to the MEMR pin; of a valid receive frame): CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 76: Polling The Cs8900A In Memory Mode

    0000h Read/Write Receive/Transmit Data (Port 0) provide the internal address of the target register to 0002h Read/Write Receive/Transmit Data (Port 1) be accessed during the current operation. The next Table 17. I/O Mode Mapping CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 77: Packetpage Data Ports 0 And 1

    (REP IN) from the I/O Mode transmit operations occur in the follow- Receive/Transmit Data Port (I/O base + 0000h) ing order (using interrupts): to transfer the frame from CS8900A memory to CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 78: Accessing Internal Registers

    If interrupts are not used, the host can poll the PacketPage Pointer Port (I/O base + 000Ah). The CS8900A to check if receive frames are present and if memory space is available for transmit. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 79: Operation

    Event reports in the queue. A read- Section 5.4 on page 90 through Section 5.5 on out of a null word (0000h) indicates that all inter- page 93 describe DMA operation. rupts have been read. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 80 Event Process applicable BufEvent report bits: RxDest, Rx128, RxMiss, BufEvent TxUnderrun, Rdy4Tx, type? RxDMAFrame, SWint. RxMISS Process RxMISS counter. TxCOL Process TxCOL counter. None of the above Service Default Figure 19. Interrupt Status Queue CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 81: Terminology: Packet, Frame, And Transfer

    CS8900A (a receive frame is said to be "accepted" The term "frame" refers to the portion of a packet when the frame is buffered, either on chip or in host from the DA to the FCS. This includes the Destina- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 82: Selecting Which Events Cause Interrupts

    (Register 17) are used to determine how * Must also meet the criteria programmed into bits 8, C, D, and E. frames will be transferred to host memory, as de- Table 19. Frame Acceptance Criteria scribed in Table 22. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 83: Receive Frame Pre-Processing

    If it fails the DA filter, the - RuntiE? frame is discarded. See Section 5.3 on page 87 for - RxDMAiE? a more detailed description of DA filtering. Pre-Processing Complete Figure 21. Receive Frame Pre-Processing CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 84: Early Interrupt Generation

    F) or the Rx128 bit (Register C, BufEvent, Bit whether or not to accept the frame by comparing B) to become set, and the host has learned about the frame with the criteria programmed into the Rx- CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 85 Host may read frame. Received? Rx128 cleared and RxOK, CRCerror or Extradata set, as appropriate. If ExtradataA, RxOKA or CRCerrorA is set, frame is accepted and Host may read frame. Figure 22. Early Interrupt Generation CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 86: Transferring Held Receive Frames

    1) The CS8900A generates an RxOK interrupt to base + 0000h, with status and length preceding the the host to signal the arrival of a good frame. frame. 2) The host reads the ISQ (PacketPage base + CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 87: Receive Frame Byte Counter

    (A receive frame is said to being received by the CS8900A from the Ethernet be "accepted" by the CS8900A when the frame (parallel frame-reception and frame-read-out data are placed in either on-chip memory, or in host tasks). CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 88: Individual Address Frames

    Individual Address frames with DA that pass the hash filter (DA[0] must be “0”) Multicast frames with DA that pass the hash filter (DA[0] must be “1”) Broadcast frames All frames Table 24. DA Filtering Options CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 89: Hash Filter

    CS8900A from incoming frame Logic 6-bit Hash Register (HR) [Hash Table Index] 6-to-64 decoder Hashed 64-input OR gate 64-bit Logical Address Filter (LAF) Written into PacketPage base + 150h Figure 23. Hash Filter Operation CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 90: Receive Dma

    DMA-only mode. Section 5.5 on page 93 describes ceived frames (along with their status and length) Auto-Switch DMA and Section 5.6 on page 96 de- in a circular buffer located in host memory space. scribes StreamTransfer. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 91: Receive-Dma-Only Operation

    Note that when in DMA mode, reading the contents frame has been received, pre-processed, and ac- of the RxEvent register will return 0000h. Status cepted, the CS8900A signals the DMA controller that a frame is to be transferred to host memory by CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 92: Committing Buffer Space To A Dmaed Frame

    CS8900A generates an interrupt when a frame is ferred as words and maintain double-word (32-bit) transferred by DMA. Figure 25 shows how a DMA alignment. Unfilled memory space between suc- Receive Frame interrupt is processed. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 93: Auto-Switch Dma

    DMA Start of Frame "Holes" due to register (PacketPage double-word base + 0126H) RxStatus - Frame 3 alignment points here. RxLength - Frame 3 Frame 3 Figure 24. Example of Frames Stored in DMA Buffer CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 94: Configuring The Cs8900A For Auto-Switch Dma

    Aonly bit (Register 3, RxCFG, bit 9) are both set, into host memory. This frees up buffer space for the the CS8900A uses DMA for all receive frames. incoming frame. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 95: Dma Channel Speed Vs. Missed Frames

    (first in, first out), the beginning of the received frame • The host processes all RxEvent and BufEvent that triggered the switch to DMA is not the first reports pending in the ISQ. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 96: Auto-Switch Dma Example

    When the CS8900A initiates a StreamTransfer cy- cle, it will continue to execute cycles as long as the 5.6.3 StreamTransfer Operation following conditions hold true: When StreamTransfer is enabled, the CS8900A will initiate a StreamTransfer cycle whenever two CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 97 Since there are no receive interrupts pending, the CS8900A exits DMA (assumes Frame 3 is still coming in). Frame 3 is completely buffered in on-chip RAM, and awaits processing by the host. Exit Example Figure 27. Example of Auto-Switch DMA CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 98: Example Of Streamtransfer

    9 Interrupts for 9 "Good" Packets Time Figure 28. Receive Example Without Stream Transfer 4 Back-to-Back Frames T > 52 us 5 Back-to-Back Frames Interrupt Request 2 Interrupts for 9 "Good" Packets Time Figure 29. Receive DMA Configuration Options CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 99: Transmit Operation

    (see Section 3.4 on page 21). The items bits may affect the packet currently being transmit- that must be configured include which physical in- ted. terface to use and which transmit events cause in- terrupts. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 100: Enabling Crc Generation And Padding

    The information written to the TxCMD register first clear the SerTxON bit (Register 13, LineCTL, tells the CS8900A how to transmit the next frame. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 101: Transmit In Poll Mode

    2) The host writes the transmit frame length to the TxLength register (memory base + 0146h in 1) The host bids for frame storage by writing the memory mode and I/O base + 0006h in I/O Transmit Command to the TxCMD register CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 102 TxBidErr, bit 7, performed in memory mode by reading Regis- in BusST register is set. ter 18, at memory base + 0138h. In I/O mode, the host must first set the PacketPage Pointer at CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 103: Completing Transmission

    BufCFG, Bit 8) is not set). Also, the Rdy4Tx bit is Force (Register 9, TxCMD, bit 8) bit. In this used with interrupts and requires the Rdy4TxiE bit case, the committed transmit frame, as well as be set. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 104 Underrun bit (Register C, BufEvent, Bit 9) is ted. The host should make TxLength = 0 when set. using the Force bit. Successful transmission is indicated when the TxOK bit (Register 8, TxEvent, Bit 8) is set. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 105: Transmit Frame Length

    Notes: 8. If the TxPadDis bit is clear and InhibitCRC is set and the CS8900A is commanded to send a frame of length less than 60 bytes, the CS8900A pads. 9. The CS8900A will not send a frame with TxLength less than 3 bytes. Table 35. Transmit Frame Length CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 106: Test Modes

    (since there is no collision signal, an SQE error will occur). AUI Collision Start transmission and observe DO+/DO- activity. Input a 10 MHz sine wave to Cl+/Cl- pins and observe collisions. Table 37. AUI Loopback and Collision Tests CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 107: Boundary Scan

    SD08-SD15 27-24, 21-18 SD0 - SD7 65-68, 71-74 MEMW RESET through all 34 pins. This test is referred to as a MEMR SLEEP "walking 0" test. Table 40. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 108: Continuity Cycle

    ISA-bus Address Enable. of AEN returns all digital output pins and bi-direc- tional pins to a high-impedance state. Figure 32 shows a complete Boundary Scan Conti- nuity Cycle. Figure 33 shows Boundary Scan timing. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 109 AEN switches low All digital output pins and AEN switches high bi-directional pins enters High-Z state TEST switches high EXIT BOUNDARY SCAN: AEN becomes ISA bus Address Enable Figure 32. Boundary Scan Continuity Cycle CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 110 BSTATUS EEDataOut SLEEP RESET ELCS copied copied copied OUTPUTS OUTPUT INPUT OUTPUTS Hi Z TEST TEST Hi Z 34 Clocks 50 Clocks 1 clock COMPLETE CONTINUITY CYCLE 85 Clocks Figure 33. Boundary Scan Timing CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 111: Characteristics/Specifications

    Hardware Standby Mode Current (Note 1) I DDSTNDBY Hardware Suspend Mode Current (Note 1) I µA DDHWSUS Software Suspend Mode Current (Note 1) I DDSWSUS Notes: 1. With digital outputs connected to CMOS loads. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 112 B24: Bi-Directional with 3-State Output and 24 mA Drive B4w: Bi-Directional with 3-State Output, Internal Weak Pullup, and 4 mA Drive O24ts: 3-State Output with 24 mA Drive O4: Output with 4 mA Drive I: Input Iw: Input with Internal Weak Pullup CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 113: Switching Characteristics

    Valid Data 16-Bit I/O Read, IOCHRDY not used DIRECTION: IN or OUT of chip SA [15:0], Valid Address AEN, SBHE IOCS16 IOR7 IOCHRDY IOR8 SD [15:0] Valid Data IOR9 16-Bit I/O Read, with IOCHRDY CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 114 Valid Data 16-Bit Memory Read, IOCHRDY not used DIRECTION: IN or OUT of chip SA [19:0], Valid Address SBHE, CHIPSEL MEMCS16 MEMR MEMR7 IOCHRDY MEMR8 SD [15:0] Valid Data MEMR9 16-Bit Memory Read, with IOCHRDY CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 115 Data Data Data 16-Bit DMA Read DIRECTION: IN or OUT of chip SA [15:0], Valid Address AEN, SBHE IOW1 IOW7 IOCS16 IOW6 IOW2 IOW3 IOW4 IOW5 SD [15:0] Valid Data In 16-Bit I/O Write CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 116 IN or OUT of chip SA [19:0], SBHE, Valid Address CHIPSEL MEMW1 MEMW6 MEMCS16 MEMW2 MEMW7 MEMW3 MEMW MEMW5 MEMW4 SD [15:0] Valid Data In 16-Bit Memory Write t TTX2 TXD± t TTX3 t TTX1 10BASE-T Transmit CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 117 RXD± t TRX1 t TRX2 t TRX5 t TRX3 t TRX4 Carrier Sense (internal) 10BASE-T Receive t LN1 t LN2 t LN3 TXD± t LN4 t LN5 RXD± t LN6 LINKLED 10BASE-T Link Integrity CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 118 ATX1 t ATX2 AUI Transmit DI± t ARX1 t ARX2 t ARX1 t ARX3 t ARX4 t ARX5 Carrier Sense (Internal) AUI Receive CI± ACL3 ACL1 ACL2 ACL2 ACL4 ACL5 Collision (Internal) AUI Collision CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 119 BPROM1 MEMR t BPROM2 t BPROM3 CSOUT External Boot PROM Access EESK t SKS t CSH t CS EECS t CSS t DIH t DIS EEData Out t DH EEData In (Read) EEPROM CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 120: 10Base-T Wiring

    24.3 49.9 30.1 60.4 37.4 Ω Ω • Note: for 3.3V operation the turns ratio on TXD+ and TXD- is 1:2.5, rt is 8 for 100 cable and the 68pF cap changes to 560pF. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 121: Aui Wiring

    (If a 20 MHz quartz crystal is used, it must meet the following specifications) Parameter Unit Parallel Resonant Frequency Resonant Frequency Error (C = 18 pF) Resonant Frequency Change Over Operating Temperature Crystal Capacitance Motional Crystal Capacitance 0.022 Series Resistance Shunt Capacitance CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 122: Physical Dimensions

    0.642 15.70 16.30 0.547 0.555 13.90 14.10 0.016 0.024 0.40 0.60 0.018 0.030 0.45 0.75 ∝ 0.000° 7.000° 0.00° 7.00° * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 123: Glossary Of Terms

    Medium Attachment Unit Management Information Base Receive Source Address or ISA System Address Bus (SA0 - SA19) Start-of-Frame Delimiter SNMP Simple Network Management Protocol Start-of-Frame Signal Quality Error Time Domain Reflectometer Transmit Unshielded Twisted Pair CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 124: Definitions

    Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot Time equals 512 bit times. Transmit Collision A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI- (AUI) are active while a packet is being transmitted. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 125: Acronyms Specific To The Cs8900A

    A method used to significantly reduce the number of interrupts to the host processor during block data transfers (Patent Pending). PacketPage A unified, highly-efficient method of controlling and getting status of a peripheral controller in I/O or Memory space. CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...

  • Page 126: Suffixes Specific To The Cs8900A

    3) The host reads BusST (Register 18) to see in the Rdy4TxNOW bit (Bit 8) is set. 9.5 Suffixes Specific to the CS8900A. These terms have meaning only at the end of a term: Accept Command Configure Control Disable Enable Indicates the number is hexadecimal Interrupt Enable Status CIRRUS LOGIC PRODUCT DATA SHEET DS271PP3...
  • Page 127 • Notes •...
  • Page 128 (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent...

This manual is also suitable for:

Crystal lan cs8900a-iqCrystal lan cs8900a-cq3Crystal lan cs8900a-iq3Crystal lan cs8900a-cq

Table of Contents