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Manuals and User Guides for Cirrus Logic CS4953xx. We have
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Cirrus Logic CS4953xx manual available for free PDF download: Hardware User Manual
Cirrus Logic CS4953xx Hardware User Manual (118 pages)
32-bit Audio DSP Family
Brand:
Cirrus Logic
| Category:
Media Converter
| Size: 2 MB
Table of Contents
Table of Contents
3
Figures
5
Chapter 1. Introduction
9
Overview
9
Chip Features
9
Figure 1-1. Cs4953Xx Chip Functional Block Diagram
10
Functional Overview of the Cs4953Xx Chip
12
DSP Core
12
Security Extension Module
12
Debug Controller (DBC)
12
Digital Audio Output (DAO1, DAO2) Controller
12
Digital Audio Input (DAI1) Controller
12
Compressed Data Input / Digital Audio Input (DAI2) Controller
12
Direct Stream Digital ® (DSD) Controller
13
General Purpose I/O
13
Parallel Control Port (Motorola/Intel Standards)
13
Serial Control Ports (SPI ™ or I 2 C ® Standards)
13
SDRAM Controller
14
Flash Controller
14
DMA Controller
14
Timers
14
Clock Manager and PLL
14
Programmable Interrupt Controller
15
Chapter 2. Operational Modes
17
Figure 2-1. Operation Mode Block Diagrams
18
Operational Mode Selection
19
Slave Boot Procedures
19
Table 2-1. Operation Modes
19
Host Controlled Master Boot
20
Figure 2-2. Host Controlled Master Boot
21
Performing a Host Controlled Master Boot (HCMB)
21
Slave Boot
23
Figure 2-3. Slave Boot Sequence
24
Performing a Slave Boot
24
Boot Messages
26
Host-Controlled Master Boot from Parallel ROM
26
Slave Boot
26
Table 2-2. SLAVE_BOOT Message for Cs4953Xx
26
Host-Controlled Master Boot from I
27
Host-Controlled Master Boot from SPI ROM
27
Messages Read from Cs4953Xx
28
Soft Reset
28
Table 2-7. SOFT_RESET Message for Cs4953Xx
28
Table 2-8. Boot Read Messages from Cs4953Xx
28
Master Boot Procedure
29
Figure 2-4. Master Boot Sequence Flowchart
29
Table 2-9. Boot Command Messages for Cs4953Xx
29
Softboot
30
Softboot Messaging
30
Table 2-10. SOFTBOOT Message
30
Softboot Procedure
31
Figure 2-5. Soft Boot Sequence Flowchart
31
Figure 2-6. Soft Boot Example Flowchart
32
Softboot Example
32
Softboot Example Steps
33
Chapter 3. Serial Control Port
35
Serial Control Port Configuration
35
I 2 C Port
36
I 2 C System Bus Description
36
Figure 3-1. Serial Control Port Internal Block Diagram
36
I 2 C Bus Dynamics
38
Figure 3-3. I 2 C Start and Stop Conditions
38
Figure 3-4. I 2 C Address with ACK and NACK
39
Figure 3-5. Data Byte with ACK and NACK
40
Figure 3-6. Repeated Start Condition with ACK and NACK
40
I2C Messaging
41
Figure 3-7. Stop Condition with ACK and NACK
41
Figure 3-8. I 2 C Write Flow Diagram
42
Performing a Serial I C Write
42
SCP1_BSY Behavior
42
I 2 C Write Protocol
43
Performing a Serial I C Read
43
Figure 3-9. I 2 C Read Flow Diagram
44
I 2 C Read Procedure
45
SCP1_IRQ Behavior
47
SPI Port
47
Figure 3-12. SPI Serial Control Port Internal Block Diagram
47
Table 3-2. Serial Control Port SPI Signals
48
Figure 3-13. Block Diagram of SPI System Bus
49
SPI Bus Dynamics
49
SPI System Bus Description
49
Figure 3-14. Address and Data Bytes
50
SPI Messaging
50
Figure 3-15. SPI Write Flow Diagram
51
Figure 3-16. SPI Write Flow Diagram
51
Performing a Serial SPI Write
51
SPI Write Protocol
51
Figure 3-17. SPI Read Flow Diagram
52
Performing a Serial SPI Read
52
SPI Read Protocol
53
Figure 3-19. Sample Waveform for SPI Read Functional Timing
54
Figure 3-20. Sample Waveform for SPI Read Functional Timing
54
SCP1_IRQ Behavior
55
Chapter 4. Parallel Control Port
57
Chapter 5. Digital Audio Input Interface
59
Digital Audio Input Port Description
59
DAI Pin Description
59
Table 5-1. Digital Audio Input Port
59
Supported DAI Functional Blocks
60
BDI Port
60
Figure 5-1. DAI Port Block Diagram
60
Table 5-2. Bursty Data Input (BDI) Pins
61
Digital Audio Formats
62
I 2 S Format
62
Left-Justified Format
62
DAI Hardware Configuration
62
Figure 5-2. I2S Format (Rising Edge Valid SCLK)
62
Figure 5-3. Left-Justified Format (Rising Edge Valid SCLK)
62
DAI Hardware Naming Convention
63
Table 5-3. Input Data Format Configuration (Input Parameter A)
63
Table 5-4. Input SCLK Polarity Configuration (Input Parameter B)
65
Table 5-5. Input LRCLK Polarity Configuration (Input Parameter C)
65
Table 5-6. Input DAI Mode Configuration (Input Parameter D)
66
Chapter 6. Direct Stream Data (DSD) Input Interface
67
Description of Digital Audio Input Port When Configured for DSD Input
67
DSD Pin Description
67
Supported DSD Functional Blocks
67
Table 6-1. Dsdl Audio Input Port
67
Figure 6-1. DSD Port Block Diagram
68
Chapter 7. Digital Audio Output Interface
69
Digital Audio Output Port Description
69
DAO Pin Description
69
Table 7-1. Digital Audio Output (DAO1 & DAO2) Pins
69
Supported DAO Functional Blocks
70
Figure 7-1. DAO Block Diagram
70
DAO Interface Formats
71
I 2 S Format
71
Left-Justified Format
71
One-Line Data Mode Format (Multichannel)
72
DAO Hardware Configuration
72
Figure 7-4. One-Line Data Mode Digital Audio Formats
72
Table 7-2. Output Clock Mode Configuration (Parameter A)
73
Table 7-3. DAO1 & DAO2 Clocking Relationship Configuration (Parameter B)
73
Table 7-4. Output DAO_SCLK/LRCLK Configuration (Parameter C)
73
Table 7-5. Output Data Format Configuration (Parameter D)
75
Table 7-6. Output DAO_LRCLK Polarity Configuration (Parameter E)
76
Table 7-7. Output DAO_SCLK Polarity Configuration (Parameter F)
76
S/PDIF Transmitter
77
Table 7-8. S/PDIF Transmitter Pins
77
Table 7-9. S/PDIF Transmitter Config
77
Table 7-10. DSP Bypass Config
77
Chapter 8. External Memory Interfaces
79
SDRAM Controller
79
Flash Memory Controller
79
Figure 8-1. SDRAM Interface Block Diagram
79
Flash Controller Interface
80
Sdram/Flash Controller Interface
80
Sdram/Flash Interface Signals
80
Table 8-1. SDRAM Interface Signals
80
Configuring Sdram/Flash Parameters
82
Table 8-2. Sdram/Flash Controller Parameters
82
Chapter 9. System Integration
89
Typical Connection Diagrams
89
Figure 9-1. LQFP-144, I 2 C Control, Serial FLASH, SDRAM, 7 Dacs
90
Figure 9-2. LQFP-144, SPI Control, Serial FLASH, SDRAM, 7 Dacs
91
Figure 9-3. LQFP-144, SPI Control, Serial FLASH, SDRAM, 8 Dacs
92
Figure 9-4. LQFP-144, I2C Control, Parallel Flash, SDRAM, 8 Dacs
93
Figure 9-5. LQFP-128, SPI Control, Parallel Flash, SDRAM, 8 Dacs
94
Figure 9-6. LQFP-128, I 2 C Control, Serial FLASH, DSD Audio Input, SDRAM, 7 Dacs
95
Figure 9-7. LQFP-144, SPI Control, Serial FLASH, DSD Audio Input, SDRAM, 7 Dacs
96
Figure 9-8. LQFP-144, SPI Control, Serial FLASH, DSD Audio Input, SDRAM, 7 Dacs
97
Pin Description
98
Power and Ground
98
Power
98
Table 9-1. Core Supply Pins
98
Table 9-2. I/O Supply Pins
98
Analog Power Conditioning
99
Decoupling
99
Ground
99
PLL Filter
99
Table 9-3. Core and I/O Ground Pins
99
Table 9-4. PLL Supply Pins
99
Pll
100
Clocking
100
Figure 9-9. PLL Filter Topology
100
Table 9-5. PLL Filter Pins
100
Table 9-6. Reference PLL Component Values
100
Control
101
Figure 9-10. Crystal Oscillator Circuit Diagram
101
Operational Mode
101
Table 9-7. DSP Core Clock Pins
101
Table 9-8. Reset Pin
102
144-Pin LQFP Pin Assigments
103
Figure 9-11. 144-Pin LQFP Pin Layout
103
128-Pin LQFP Pin Assigments
104
Figure 9-12. 128-Pin LQFP Pin Layout
104
Pin Assignments
105
Revision History
117
DS732UM7 Copyright 2008 Cirrus Logic, Inc
118
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