Switching Characteristics - Control Port - Spi Format; Figure 9.Control Port Timing - Spi Format - Cirrus Logic CS44600 Manual

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C
CCLK Clock Frequency
CS High Time between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For f <1 MHz.
sck
DS633F1
Parameter
CS
t css
CCLK
t r2
CDIN
t dsu
CDOUT
Figure 9. Control Port Timing - SPI Format
Symbol
f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
(Note 19) t
dh
t
pd
t
r1
t
f1
(Note 20) t
r2
(Note 20) t
f2
t scl t sch
t f2
t dh
t pd
CS44600
= 30 pF)
L
Min Typ Max
0 - 6.0
1.0 - -
20 - -
66 - -
66 - -
40 - -
15 - -
- - 50
- - 25
- - 25
- - 100
- - 100
t csh
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15