User Manuals: Cirrus Logic CS44600-DQZR Controller

Manuals and User Guides for Cirrus Logic CS44600-DQZR Controller. We have 1 Cirrus Logic CS44600-DQZR Controller manual available for free PDF download: Manual

Cirrus Logic CS44600-DQZR Manual (76 pages)

6-Channel Digital Amplifier Controller

Brand: Cirrus Logic | Category: Controller | Size: 0 MB

Table of Contents
3
Characteristics and Specifications
8
Specified Operating Conditions
8
Absolute Maximum Ratings
8
DC Electrical Characteristics
9
Digital Interface Characteristics
9
Pwm Output Performance Characteristics
10
Figure 1.Performance Characteristics Evaluation Active Filter Circuit
10
Pwm Filter Characteristics
11
Switching Characteristics - Xti
11
Figure 2.XTI Timings
11
Switching Characteristics - Sys_Clk
12
Switching Characteristics - Pwmouta1-B3
12
Switching Characteristics - Ps_Sync
12
Figure 3.SYS_CLK Timings
12
Figure 4.Pwmoutxx Timings
12
Figure 5.PS_SYNC Timings
12
Switching Characteristics - Dai Interface
13
Figure 6.Serial Audio Interface Timing
13
Figure 7.Serial Audio Interface Timing - TDM Mode
13
Switching Characteristics - Control Port - I²C Format
14
Figure 8.Control Port Timing - I²C Format
14
Switching Characteristics - Control Port - Spi Format
15
Figure 9.Control Port Timing - SPI Format
15
Pin Descriptions
16
Figure 10.CS44600 Pinout Diagram
16
I/O Pin Characteristics
19
Typical Connection Diagrams
20
Figure 11.Typical Full-Bridge Connection Diagram
20
Figure 12.Typical Half-Bridge Connection Diagram
21
Applications
22
Overview
22
Feature Set Summary
22
Clock Generation
23
Figure 13.CS44600 Data Flow Diagram (Single Channel Shown)
23
Fsin Domain Clocking
24
Fsout Domain Clocking
24
Figure 14.Fundamental Mode Crystal Configuration
24
Table 1. Common DAI_MCLK Frequencies
24
Figure 15.3Rd Overtone Crystal Configuration
25
Figure 16.CS44600 Internal Clock Generation
25
Fsin Clock Domain Modules
26
Digital Audio Input Port
26
Table 2. DAI Serial Audio Port Channel Allocations
26
Figure 17.I²S Serial Audio Formats
27
Figure 18.Left-Justified Serial Audio Formats
27
Figure 19.Right-Justified Serial Audio Formats
28
Figure 20.One Line Mode #1 Serial Audio Format
28
Figure 21.One Line Mode #2 Serial Audio Format
29
Figure 22.TDM Mode Serial Audio Format
29
Auto Rate Detect
30
Emphasis
30
Figure 23.De-Emphasis Curve
30
Fsout Clock Domain Modules
31
Sample Rate Converter
31
Load Compensation Filter
31
Digital Volume and Mute Control
31
Table 3. Load Compensation Example Settings
31
Peak Detect / Limiter
32
PWM Engines
32
Interpolation Filter
33
Quantizer
33
Modulator
33
PWM Outputs
33
Table 4. Typical PWM Switch Rate Settings
33
4.5.10 Power Supply Rejection (PSR) Real-Time Feedback
34
Control Port Description and Timing
35
SPI Mode
35
Figure 24.Control Port Timing in SPI Mode
35
I²C Mode
36
Figure 25.Control Port Timing, I²C Slave Mode Write
36
Figure 26.Control Port Timing, I²C Slave Mode Read
36
Gpios
37
Host Interrupt
37
Power Supply, Grounding, and Pcb Layout
38
Figure 27.Recommended CS44600 Power Supply Decoupling Layout
38
Figure 28.Recommended CS44600 Crystal Circuit Layout
39
Figure 29.Recommended PSR Circuit Layout
40
Reset and Power-Up
41
PWM Popguard® Transient Control
41
Recommended Power-Up Sequence
41
Recommended PSR Calibration Sequence
42
Recommended Power-Down Sequence
43
Figure 30.PSR Calibration Sequence
43
Register Quick Reference
44
Register Description
48
Memory Address Pointer (MAP)
48
Increment (INCR)
48
Memory Address Pointer (Mapx)
48
CS44600 I.D. and Revision Register (Address 01H) (Read Only)
48
Chip I.D. (Chip_Idx)
48
Chip Revision (Rev_Idx)
48
Clock Configuration and Power Control (Address 02H)
49
Enable SYS_CLK Output (EN_SYS_CLK)
49
SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0])
49
PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0])
49
Power down XTAL (PDN_XTAL)
49
Power down Output Mode (PDN_OUTPUT_MODE)
50
Power down (PDN)
50
PWM Channel Power down Control (Address 03H)
50
Power down PWM Channels (PDN_PWMB3:PDN_PWMA1)
50
Misc. Configuration (Address 04H)
51
Digital Interface Format (DIFX)
51
AM Frequency Hopping (AM_FREQ_HOP)
51
Freeze Controls (FREEZE)
51
Table 5. Digital Audio Interface Formats
51
Emphasis Control (DEM[1:0])
52
Ramp Configuration (Address 05H)
52
Ramp-Up/Down Setting (RAMP[1:0])
52
Ramp Speed (RAMP_SPD[1:0])
52
Volume Control Configuration (Address 06H)
53
Single Volume Control (SNGVOL)
53
Soft Ramp and Zero Cross Control (SZC[1:0])
53
Enable 50% Duty Cycle for Mute Condition (MUTE_50/50)
53
Soft Ramp-Down on Interface Error (SRD_ERR)
54
Soft Ramp-Up on Recovered Interface Error (SRU_ERR)
54
Auto-Mute (AMUTE)
54
Master Volume Control - Integer (Address 07H)
55
Master Volume Control - Integer (MSTR_IVOL[7:0])
55
Master Volume Control - Fraction (Address 08H)
55
Master Volume Control - Fraction (MSTR_FVOL[1:0])
55
Table 6. Master Integer Volume Settings
55
Table 7. Master Fractional Volume Settings
56
Channel XX Volume Control - Integer (Addresses 09H - 0Eh)
57
Channel Volume Control - Integer (Chxx_Ivol[7:0])
57
Channel XX Volume Control1 - Fraction (Address 11H)
57
Channel XX Volume Control2 - Fraction (Address 12H)
57
Channel Volume Control - Fraction (CHXX_FVOL[1:0])
57
Table 8. Channel Integer Volume Settings
57
Channel Mute (Address 13H)
58
Channel Invert (Address 14H)
58
Table 9. Channel Fractional Volume Settings
58
Peak Limiter Control Register (Address 15H)
59
Peak Signal Limit All Channels (LIMIT_ALL)
59
Peak Signal Limiter Enable (LIMIT_EN)
59
Limiter Attack Rate (Address 16H)
59
Attack Rate (ARATE[7:0])
59
Limiter Release Rate (Address 17H)
60
Release Rate (RRATE[7:0])
60
Chnl XX Load Compensation Filter - Coarse Adjust (Addresses 18H, 1Ah, 1Ch, 1Eh, 20H, 22H)
60
Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0])
60
Table 10. Limiter Attack Rate Settings
60
Table 11. Limiter Release Rate Settings
60
Chnl XX Load Compensation Filter - Fine Adjust (Addresses 19H, 1Bh, 1Dh, 1Fh, 21H, 23H)
61
Channel Compensation Filter - Fine Adjust (CHXX_FINE[5:0])
61
Interrupt Mode Control (Address 28H)
61
Interrupt Pin Control (INT1/INT0)
61
Table 12. Channel Load Compensation Filter Coarse Adjust
61
Table 13. Channel Load Compensation Filter Fine Adjust
61
Overflow Level/Edge Select (OVFL_L/E)
62
Interrupt Mask (Address 29H)
62
Interrupt Status (Address 2Ah) (Read Only)
62
SRC Unlock Interrupt (SRC_UNLOCK)
62
SRC Lock Interrupt (SRC_LOCK)
63
Ramp-Up Complete Interrupt (RMPUP_DONE)
63
Ramp-Down Complete Interrupt (RMPDN_DONE)
63
Mute Complete Interrupt (Mute_Done)
63
Channel over Flow Interrupt (OVFL_INT)
63
GPIO Interrupt Condition (GPIO_INT)
63
Channel over Flow Status (Address 2Bh) (Read Only)
64
7.23.1 Chxx_Ovfl
64
GPIO Pin In/Out (Address 2Ch)
64
GPIO In/Out Selection (GPIOX_I/O)
64
GPIO Pin Polarity/Type (Address 2Dh)
64
GPIO Polarity/Type Selection (GPIOX_P/T)
64
GPIO Pin Level/Edge Trigger (Address 2Eh)
65
GPIO Level/Edge Input Sensitive (GPIOX_L/E)
65
GPIO Status Register (Address 2Fh)
65
GPIO Pin Status (GPIOX_STATUS)
65
GPIO Interrupt Mask Register (Address 30H)
66
GPIO Pin Interrupt Mask (M_GPIOX)
66
PWM Configuration Register (Address 31H)
66
Over Sample Rate Selection (OSRATE)
66
Channels A1 and B1 Output Configuration (A1/B1_OUT_CNFG)
66
Channels A2 and B2 Output Configuration (A2/B2_OUT_CNFG)
66
Channel A3 Output Configuration (A3_OUT_CNFG)
67
Channel B3 Output Configuration (B3_OUT_CNFG)
67
PWM Minimum Pulse Width Register (Address 32H)
67
Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)
67
Minimum PWM Output Pulse Settings (MIN_PULSE[4:0])
67
PWMOUT Delay Register (Address 33H)
68
Differential Signal Delay (DIFF_DLY[2:0])
68
Channel Delay Settings (CHNL_DLY[4:0])
68
Table 14. PWM Minimum Pulse Width Settings
68
Table 15. Differential Signal Delay Settings
68
Table 16. Channel Delay Settings
68
PSR and Power Supply Configuration (Address 34H)
69
Power Supply Rejection Enable (PSR_EN)
69
Figure 31.PWM Output Delay
69
Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0])
70
Decimator Shift/Scale (Addresses 35H, 36H, 37H)
70
Decimator Shift (DEC_SHIFT[2:0])
70
Table 17. Power Supply Sync Clock Divider Settings
70
Decimator Scale (DEC_SCALE[18:0])
71
Decimator Outd (Addresses 3Bh, 3Ch, 3Dh)
71
Decimator Outd (DEC_OUTD[23:0])
71
Table 18. Decimator Shift/Scale Coefficient Calculation Examples
71
Parameter Definitions
72
References
73
10.Package Dimensions
74
Figure 32.64-Pin LQFP Package Drawing
74
11.Thermal Characteristics
75
12.Ordering Information
75
13.Revision History
75

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