Cirrus Logic WM8940 Manual page 77

REGISTER BIT LABEL
ADDRESS
5:0 PLLK[23:18]
38 (26h) 15:9
8:0 PLLK[17:9]
39 (27h) 15:9
8:0 PLLK[8:0]
40 (28h) 15:0
41 (29h) 15:0
42 (2Ah) 15:2
1 ALCZC
0
43 (2Bh) 15:0
44 (2Ch) 15:9
8 MBVSEL
7:4
3 AUXMODE
2 AUX2INPPGA
1 MICN2INPPGA
0 MICP2INPPGA
45 (2Dh) 15:8
7 INPPGAZC
6 INPPGAMUTE
Rev 4.4
DEFAULT
001100 Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
00h Reserved
010010011 Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
00h Reserved
011101001 Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
0000h Reserved
0000h Reserved
0 Reserved
0 (zero ALC uses zero cross detection circuit.
cross off)
0 = Disabled (recommended)
1 = Enabled
0 Reserved
0000h Reserved
00h Reserved
0 Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.75 * AVDD
0h Reserved
0 Auxiliary Input Mode
0 = inverting buffer
1 = mixer (on-chip input resistor bypassed)
0 Select AUX amplifier output as input PGA signal
source.
0=AUX not connected to input PGA
1=AUX connected to input PGA amplifier negative
terminal.
1 Connect MICN to input PGA negative terminal.
0=MICN not connected to input PGA
1=MICN connected to input PGA amplifier negative
terminal.
0 Connect input PGA amplifier positive terminal to MICP
or VMID.
0 = input PGA amplifier positive terminal connected to
VMID
1 = input PGA amplifier positive terminal connected to
MICP through variable resistor string
00h Reserved
0 Input PGA zero cross enable:
0=Update gain when gain register changes
1=Update gain on 1
write.
1 Mute control for input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from the
following input BOOST stage).
DESCRIPTION
st
zero cross after gain register
WM8940
REFER TO
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
ALC Control 4
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
77