Control Interface Timing - 3-Wire Mode - Cirrus Logic WM8940 Manual

CONTROL INTERFACE TIMING – 3-WIRE MODE
Test Conditions
DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T
MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
Rev 4.4
CSB/GPIO
SCLK
SDIN
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
t
CSL
t
SCY
t t
SCH SCL
t t
DSU DHO
= +25
A
SYMBOL MIN
t 80
SCS
t 200
SCY
t 80
SCL
t 80
SCH
t 40
DSU
t 40
DHO
t 40
CSL
t 40
CSH
t 40
CSS
t 0
ps
WM8940
t
CSH
t
CSS
t
SCS
LSB
o
C, Slave Mode, fs = 48kHz,
TYP MAX UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
5 ns
17