Selectable High Pass Filter - Cirrus Logic WM8940 Manual

26
The ADC is enabled by the ADCEN register bit.
REGISTER BIT
ADDRESS
R2 0
Power
management 2
Table 11 ADC Enable
The polarity of the output signal can also be changed under software control using the ADCPOL
register bit.
REGISTER BIT
ADDRESS
R14 0
ADC Control
Table 12 ADC Polarity

SELECTABLE HIGH PASS FILTER

A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes
controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of
3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable
via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 14.
REGISTER BIT
ADDRESS
R14
8
ADC Control
7
6:4
Table 13 ADC Filter Select
HPFCUT
SR=101/100
8 11.025
000
82 113
001
102 141
010
131 180
011
163 225
100
204 281
101
261 360
110
327 450
111
408 563
Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1)
Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are
set correctly for the actual sample rate as shown in Table 14.
LABEL DEFAULT
ADCEN 0 0 = ADC disabled
1 = ADC enabled
LABEL DEFAULT
ADCPOL 0
LABEL DEFAULT
HPFEN 1 High Pass Filter Enable
0=disabled
1=enabled
HPFAPP 0 Select audio mode or application mode
0=Audio mode (1
1=Application mode (2
HPFCUT)
HPFCUT 000 Application mode cut-off frequency
See Table 14 for details.
FS (KHZ)
SR=011/010
12 16 22.05 24
122 82 113 122
153 102 141 153
196 131 180 196
245 163 225 245
306 204 281 306
392 261 360 392
490 327 450 490
612 408 563 612
WM8940
DESCRIPTION
DESCRIPTION
0=normal
1=inverted
DESCRIPTION
st
order, fc = ~3.7Hz)
nd
order, fc =
SR=001/000
32 44.1 48
82 113 122
102 141 153
131 180 196
163 225 245
204 281 306
261 360 392
327 450 490
408 563 612
Rev 4.4