Cirrus Logic WM8940 Manual page 52

52
FRAME
BCLK
DACDAT /
1 2
ADCDAT
MSB
Figure 26 Right Justified Audio Interface (assuming n-bit word length)
2
In I S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
FRAME
BCLK
1 BCLK
DACDAT
1 2 3
/ADCDAT
MSB
2
Figure 27 I S Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1
rising edge of BCLK (selectable by FRAMEP) following a rising edge of FRAME. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
FRAMEP should be set to 0 in this mode.
1 BCLK
FRAME
BCLK
DACDAT /
1 2 3
ADCDAT
MSB
Input Word Length (WL)
Figure 28 DSP/PCM Mode Audio Interface (Mode A, FRAMEP=0)
1/fs
LEFT
PHASE
3 n
n-2 n-1
LSB
1/fs
LEFT
PHASE
n
n-2 n-1
LSB
1/fs
n-2 n-1 n
LSB
WM8940
RIGHT
PHASE
RIGHT
PHASE
st nd
(Mode B) the 2 (Mode A)
Rev 4.4