Cirrus Logic WM8940 Manual page 31

Rev 4.4
REGISTER BIT LABEL
ADDRESS
R34 (22h) 8 ALCMODE
ALC Control 3
7:4 ALCDCY
[3:0]
3:0 ALCATK
[3:0]
R42 (2Ah) 1 ALCZC
ALC Control 4
Table 20 ALC Control Registers
NOTE: The Input PGA Volume register R45 must be written with the INPPGAMUTE bit R45[6] set to 0
before setting ALCSEL bit R32[8] to 1.
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input
gain update must be made by writing to the INPPGAVOLL/R register bits.
DEFAULT DESCRIPTION
0 Determines the ALC mode of operation:
0 = ALC mode (Normal Operation)
1 = Limiter mode.
0011 Decay (gain ramp-up) time
(26ms/6dB) (ALCMODE ==0)
Per step
0000 410us
0001 820us
0010 1.64ms
... (time doubles with every step)
1010 420ms
or
higher
0011 Decay (gain ramp-up) time
(5.8ms/6dB) (ALCMODE ==1)
Per step
0000 90.8us
0001 182us
0010 363us
... (time doubles with every step)
1010 93ms
0010 ALC attack (gain ramp-down) time
(3.3ms/6dB) (ALCMODE == 0)
Per step
0000 104us
0001 208us
0010 416us
... (time doubles with every step)
1010 or 106ms
higher
0010 ALC attack (gain ramp-down) time
(726us/6dB) (ALCMODE == 1)
Per step
0000 22.7us
0001 45.4us
0010 90.8us
... (time doubles with every step)
1010 or 23.2ms
higher
0 (zero cross ALC uses zero cross detection circuit.
off)
0 = Disabled (recommended)
1 = Enabled
WM8940
Per 6dB 90% of
range
3.38ms 23.6ms
6.56ms 47.2ms
13.1ms 94.5ms
3.36s 24.2s
Per 6dB 90% of
range
726us 5.23ms
1.45ms 10.5ms
2.91ms 20.9ms
744ms 5.36s
Per 6dB 90% of
range
832us 6ms
1.66ms 12ms
3.33ms 24ms
852ms 6.13s
Per 6dB 90% of
range
182.4us 1.31ms
363us 2.62ms
726us 5.23ms
186ms 1.34s
31