Register Bits By Address - Cirrus Logic WM8940 Manual

REGISTER BITS BY ADDRESS

Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
REGISTER BIT LABEL
ADDRESS
0 (00h) [15:0] RESET /
CHIP_ID
1 (01h) 15:9
8 VMID_OP_EN
7 LVLSHIFT_EN
6 AUXEN
5 PLLEN
4 MICBEN
3 BIASEN
2:0 DEVICE_REVIS
ION
2 BUFIOEN
1:0 VMIDSEL
2 (02h) 15:5
4 BOOSTEN
3
2 INPPGAEN
1
0 ADCEN
3 (03h) 15:8
Rev 4.4
DEFAULT
N/A Writing to this register will apply a software reset.
Reading from this register will return the device id
00 Reserved
0 Enables the non-VMID derived bias current generator
without enabling the VMID buffer. This bit must be set
to 1 if output amplifiers are to be enabled before VMID
is active. Once VMID and VMID buffer are enabled this
bit can be left set to 0 or left set to 1.
0 Enable bit for the level shifters. 1 for normal operation,
0 for standby.
0 Auxiliary input buffer enable
0 = OFF
1 = ON
0 PLL enable
0=PLL off
1=PLL on
0 Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
0 Analogue amplifier bias control
0=Disabled
1=Enabled
000 Readback from this register will return the device
revision in this position
0 Enable bit for the VMID buffer. The VMID buffer is
used to maintain a buffered VMID voltage on all
analogue input and output pins. 1. for normal operation
0. for standby (where inputs and outputs settle to
GND).
00 Reference string impedance to VMID pin:
00=off (open circuit)
01=50kΩ
10=250kΩ
11=5kΩ
000h Reserved
0 Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
0 Reserved
0 Input microphone PGA enable
0 = disabled
1 = enabled
0 Reserved
0 ADC Enable Control
0 = ADC disabled
1 = ADC enabled
00h Reserved
DESCRIPTION
WM8940
REFER TO
Resetting the
Chip /
Control Interface
Power
Management
Power
Management
Auxiliary Inputs
Master Clock and
Phase Locked
Loop (PLL)
Microphone
Biasing Circuit
Power
Management
Control Interface
Enabling the
Outputs
Power
Management
Input Boost
Input Signal Path
Analogue to
Digital Converter
(ADC)
69