Signal Timing Requirements; System Clock Timing - Cirrus Logic WM8940 Manual

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK
Figure 1 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T
PARAMETER
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
Note 1:
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
14
t
MCLKL
t
MCLKH
t
MCLKY
SYMBOL CONDITIONS
T MCLK=SYSCLK (=256fs)
MCLKY
MCLK input to PLL
T
MCLKDS
o
= +25 C
A
MIN TYP
81.38
Note 1
20
60:40
WM8940
MAX UNIT
ns
ns
40:60
Rev 4.4