Cirrus Logic WM8940 Manual page 76

REGISTER BIT LABEL
ADDRESS
31(1Fh) 15:0
32 (20h) 15:10 ALCGAIN [5:0]
9
8 ALCSEL
7:6
5:3 ALCMAX
2:0 ALCMIN
33 (21h) 15:8
7:4 ALCHLD
3:0 ALCLVL
34 (22h) 15:9
8 ALCMODE
7:4 ALCDCY
3:0 ALCATK
35 (23h) 15:4
3 NGEN
2:0 NGTH
36 (24h) 15:8
7 PLL_POWERD
OWN
6 FRACEN
5:4 PLLPRESCALE 00
3:0 PLLN[3:0]
37 (25h) 15:6
76
DEFAULT
0000h Reserved
000000 Readback from this register will return the ALC gain in
this position
0 Reserved
0 ALC function select
0=ALC disabled
1=ALC enabled
00 Reserved
111 Set Maximum Gain of PGA
000 Set minimum gain of PGA
000h Reserved
000 ALC hold time before gain is increased.
1011 ALC threshold level. Sets the desired signal level.
00h Reserved
0 Determines the ALC mode of operation:
0=Normal mode
1=Limiter mode.
0011 Decay (gain ramp-up) time
0010 ALC attack (gain ramp-down) time
000h Reserved
0 Noise gate function enable
1 = enable
0 = disable
000 Noise gate threshold
00h Reserved
0 PLL POWER
0=On
1=Off
1 Fractional Divide within the PLL
0=Disabled (Lower Power)
1=Enabled
00 = MCLK input multiplied by 2
01 = MCLK input not divided
10 = Divide MCLK by 2 before input to PLL
11 = Divide MCLK by 4 before input to PLL
1100 Integer (N) part of PLL input/output frequency ratio.
Use values greater than 5 and less than 13.
000h Reserved
DESCRIPTION
WM8940
REFER TO
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Input Limiter /
Automatic Level
Control (ALC)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Rev 4.4