Audio Interface Timing - Slave Mode - Cirrus Logic WM8940 Manual

AUDIO INTERFACE TIMING – SLAVE MODE
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T
24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
FRAME set-up time to BCLK rising edge
FRAME hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
DACDAT set-up time to BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
Note:
BCLK period should always be greater than or equal to MCLK period.
16
t
BCH
BCLK
FRAME
DACDAT
ADCDAT
Figure 3 Digital Audio Data Timing – Slave Mode
t
BCL
t
BCY
t t t
DS LRH LRSU
t t
DD DH
o
=+25 C, Slave Mode, fs=48kHz, MCLK= 256fs,
A
SYMBOL MIN
t 81.38
BCY
t 32.55
BCH
t 32.55
BCL
t 10
LRSU
t 10
LRH
t 10
DH
t 10
DS
t
DD
WM8940
TYP MAX UNIT
ns
ns
ns
ns
ns
ns
ns
15 ns
Rev 4.4