Cirrus Logic WM8940 Manual page 56

f*2
MCLK
f/2
f/4
CSB/GPIO
...
GPIOSEL
R8[2:1]
Figure 30 PLL and Clock Select Circuit
56
PLLPRESCALE
R36[5:4]
f
f
1
PLL1 2
f/4
R=f /f
2 1
f/N
OPCLKDIV
R8[5:4]
The PLL frequency ratio R = f /f
2
N = int R
24
K = int (2 (R - N))
N controls the ratio of the division, and K the fractional part.
The PLL output then passes through a fixed divide by 4, and can also be further divided by
MCLKDIV[3:0] (see figure 34). The divided clock (SYSCLK) can be used to clock the WM8940 DSP.
REGISTER BIT
ADDRESS
R36 7 PLL_POWERDOWN
PLL N value
6 FRACEN
5:4 PLLPRESCALE
3:0 PLLN
R37 5:0 PLLK [23:18]
PLL K value 1
R38 8:0 PLLK [17:9]
PLL K Value 2
R39 8:0 PLLK [8:0]
PLL K Value 3
Table 47 PLL Frequency Ratio Control
SYSCLK
(=256fs)
f
PLLOUT
f/N
CLKSEL
R6[8]
MCLKDIV
R6[7:5]
(see Figure 30) can be set using the register bits PLLK and PLLN:
1
LABEL DEFAULT
0
1
00
1100
0Ch
093h
0E9h
WM8940
ADC
f/4
DAC
f/4
MS
R6[0]
FRAME
MASTER
MODE
BCLK
MS
BCLKDIV
R6[0]
R6[4:2]
DESCRIPTION
PLL POWER
0=ON
1=OFF
Fractional Divide within the PLL
0=Disabled (Lower Power)
1=Enabled
00 = MCLK input multiplied by 2
01 = MCLK input not divided
10 = Divide MCLK by 2 before input to
PLL
11 = Divide MCLK by 4 before input to
PLL
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
Rev 4.4