Integer N Division; Fractional K Mode; Example Pll Configuration - Cirrus Logic WM8940 Manual

INPUT CLOCK DESIRED PLL OUTPUT
(F )
1
11.2896MHz
12.2880MHz
Table 48 PLL Modes of Operation (Integer N mode)
Rev 4.4

INTEGER N DIVISION

The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12.
If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low
power operation.
DIVISION
(F ) REQUIRED (R)
2
90.3168MHz
98.3040MHz

FRACTIONAL K MODE

The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up to
1/224). If these are used then FRAC_EN must be set. The relationship between the required division
R, the fractional division K[23:0] and the integer division N[3:0] is:
( R – N)
24
K = 2
where 0 < (R – N) < 1 and K is rounded to the nearest whole number.

EXAMPLE PLL CONFIGURATION:

PLL input clock (f ) is 12MHz and the required clock (SYSCLK) is 12.288MHz.
1
R should be chosen to ensure 5 < N < 13. There is a fixed divide by 4 in the PLL and a selectable
divider (MCLKDIV[3:0]) after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f
R = 98.304 / 12 = 8.192
N = int R = 8
x (8.192 – 8)) = 3221225 = 3126E9h
24
K = int (2
So N[3:0] will be 8h and K[23:0] will be 3126E9h to produce the desired 98.304MHz clock.
The PLL performs best when f
2
are shown in Table 49.
FRACTIONAL
DIVISION (K)
8 0
8 0
= 4 * 2 * 12.288MHz = 98.304MHz.
2
is around 90MHz. Its stability peaks at N=8. Some example settings
WM8940
INTEGER SDM
DIVISION (N)
8 0
8 0
57