Cirrus Logic WM8940 Manual page 71

REGISTER BIT LABEL
ADDRESS
0
5 (05h) 15:7
6 DAC_LOOPBA
CK
5 WL8
4:3 DAC_COMP
2:1 ADC_COMP
0 ADC_LOOPBA
CK
6 (06h) 15:9
8 CLKSEL
7:5 MCLKDIV
4:2 BCLKDIV
1
0 MS
7 (07h) 15:7
Rev 4.4
DEFAULT
0 Reserved
0000 Reserved
0 Digital loopback function
0=No DAC loopback
1=Loopback enabled, DAC data input is fed directly
into ADC data output.
0 8 Bit Word Length for companding
0=Word Length controlled by WL
1=8 bits
00 DAC companding
00=off
01=reserved
10=µ-law
11=A-law
00 ADC companding
00=off
01=reserved
10=µ-law
11=A-law
0 Digital loopback function
0=No ADC loopback
1=Loopback enabled, ADC data output is fed directly
into DAC data input.
00h Reserved
1 Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
010 Sets the scaling for either the MCLK or PLL clock
output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
000 Configures the BCLK and FRAME output frequency,
for use when the chip is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
0 Reserved
0 Sets the chip to be master over FRAME and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs generated by
the WM8940 (MASTER)
00000 Reserved
DESCRIPTION
WM8940
REFER TO
Digital Audio
Interfaces
Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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