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Cirrus Logic WM8940 Manual

Mono codec with speaker driver
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Mono CODEC with Speaker Driver

DESCRIPTION

The WM8940 is a low power, high quality mono CODEC
designed for portable applications such as digital still cameras
or camcorders.
The device integrates support for a differential or single ended
mic, and includes drivers for speakers or headphone, and
mono line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required.
Advanced Sigma Delta Converters are used along with digital
decimation and interpolation filters to give high quality audio at
sample rates from 8 to 48ks/s. A selectable high pass filter and
four fully-programmable notch filters are available in the ADC
path. An advanced mixed signal ALC function with noise gate
is provided, while readback of PGA gain during ALC operation
is supported. The digital audio interface supports A-law and -
law companding.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8940 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control using the selectable two
or three wire control interface.
WM8940 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area, with
high thermal performance.
http://www.cirrus.com

FEATURES

•
Mono CODEC:
•
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz
•
DAC SNR 98dB, THD -84dB ('A'-weighted @ 8 – 48ks/s)
•
ADC SNR 94dB, THD -80dB ('A'-weighted @ 8 – 48ks/s)
•
On-chip Headphone/Speaker Driver
-
40mW output power into 16
-
BTL speaker drive 0.4W into 8
•
Additional MONO Line output
•
Multiple analogue or 'Aux' inputs, plus analogue bypass path
•
Mic Preamps:
•
Differential or single end Microphone Interface
-
Programmable preamp gain
-
Pseudo differential inputs with common mode rejection
-
Programmable ALC / Noise Gate in ADC path
•
Low-noise bias supplied for electret microphones
OTHER FEATURES
•
Digital Playback Limiter
•
Programmable high pass filter (wind noise reduction)
•
4 notch filters (narrowband noise suppression)
•
On-chip PLL
•
Low power, low voltage
-
2.5V to 3.6V (digital: 1.71V to 3.6V)
•
4x4x0.9mm 24 lead QFN package

APPLICATIONS

•
Digital still cameras and camcorders
•
General purpose mono audio CODEC
Copyright © Cirrus Logic, Inc., 2006–2022
(All Rights Reserved)
WM8940
Rev 4.4
JAN 2022

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Summary of Contents for Cirrus Logic WM8940

  • Page 1: Description

    Mono CODEC with Speaker Driver DESCRIPTION FEATURES • Mono CODEC: The WM8940 is a low power, high quality mono CODEC • Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz designed for portable applications such as digital still cameras •...

  • Page 2: Block Diagram

    WM8940 BLOCK DIAGRAM analogue inputs DBVDD DCVDD DGND SPKGND SPKVDD WM8940 BYPASS PATH 0dB/10dB INPUT OUTPUTS DSP CORE BOOST INPUT MIXER MONOOUT DIGITAL FILTERS -12dB to +6dB, 3dB steps NOISY -12dB to +35.25dB, DIGITAL Volume 0.75dB steps FILTERS MICN 0dB or +20dB...

  • Page 3: Table Of Contents

    WM8940 TABLE OF CONTENTS DESCRIPTION ........................ 1 FEATURES ........................1 APPLICATIONS ......................1 BLOCK DIAGRAM ......................2 TABLE OF CONTENTS ....................3 PIN CONFIGURATION ....................6 ORDERING INFORMATION ................... 6 PIN DESCRIPTION ......................7 ABSOLUTE MAXIMUM RATINGS ................. 8 RECOMMENDED OPERATING CONDITIONS .............. 8 ELECTRICAL CHARACTERISTICS ................
  • Page 4 WM8940 MINIMUM AND MAXIMUM GAIN ..............................35 ALC HOLD TIME (NORMAL MODE ONLY) ..........................36 PEAK LIMITER ....................................38 NOISE GATE (NORMAL MODE ONLY) ............................39 OUTPUT SIGNAL PATH ......................41 DIGITAL HI-FI DAC VOLUME CONTROL ............................ 41 HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC) ........................42 AUTOMUTE ....................................
  • Page 5 WM8940 POP MINIMISATION ........................ 67 REGISTER MAP ......................68 REGISTER BITS BY ADDRESS ....................69 DIGITAL FILTER CHARACTERISTICS ............... 80 TERMINOLOGY ........................80 DAC FILTER RESPONSES ..................... 81 ADC FILTER RESPONSES ..................... 81 HIGHPASS FILTER ......................... 82 NOTCH FILTERS AND LOW-PASS FILTER ................82 NOTCH FILTER WORKED EXAMPLE ..................

  • Page 6: Pin Configuration

    WM8940 PIN CONFIGURATION MICBIAS SPKGND AVDD SPKOUTP AGND MONOOUT DCVDD MODE / GPIO DBVDD SDIN SCLK DGND TOP VIEW ORDERING INFORMATION ORDER CODE TEMPERATURE PACKAGE MOISTURE PACKAGE BODY RANGE SENSITIVITY TEMPERATURE LEVEL WM8940CGEFL/V -25C to +85C 24-lead QFN (4x4x0.9mm) MSL3...

  • Page 7: Pin Description

    WM8940 PIN DESCRIPTION NAME TYPE DESCRIPTION Analogue Output Microphone bias MICBIAS Supply Analogue supply AVDD AGND Supply Analogue ground DCVDD Supply Digital Supply (Core) DBVDD Supply Digital supply (Input/Output) Supply Digital ground DGND Digital Output ADC digital audio data output...

  • Page 8: Absolute Maximum Ratings

    Proper ESD precautions must be taken during handling and storage of this device. Cirrus Logic tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity.

  • Page 9: Electrical Characteristics

    WM8940 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Microphone Input PGA Inputs (MICN, MICP) INPPGAVOL and PGABOOST = 0dB Full-scale Input Signal Level –...
  • Page 10 WM8940 Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, T = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS UNIT Digital to Analogue Converter (DAC) to MONO Output with 10k / 50pF load and DACVOL 0dB...

  • Page 11: Terminology

    WM8940 TERMINOLOGY Full-scale input and output levels scale in relation to AVDD or SPKVDD depending upon the input or output used. For example, when AVDD = 3.3V, 0dBFS = 1V (0dBV). When AVDD < 3.3V the absolute level of 0dBFS will decrease with a linear relationship to AVDD.

  • Page 12: Audio Paths Overview

    WM8940 AUDIO PATHS OVERVIEW Rev 4.4...

  • Page 13: Power Consumption

    WM8940 POWER CONSUMPTION Typical current consumption for various scenarios is shown below. AVDD SPKVDD DCVDD DBVDD TOTAL MODE (3V3) (3V3) (1.8V) (1.8V) POWER (MW) Power OFF (No Clocks) 0.038 0.126 Sleep (VMID maintained, No Clocks) 0.190 0.627 Mono Record (MIC input, +20dB gain, 8kHz, quiescent) SLAVE 14.3...

  • Page 14: Signal Timing Requirements

    WM8940 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLKL MCLK MCLKH MCLKY Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 PARAMETER SYMBOL CONDITIONS UNIT System Clock Timing Information MCLK=SYSCLK (=256fs) 81.38 MCLKY MCLK cycle time...

  • Page 15: Audio Interface Timing - Master Mode

    WM8940 AUDIO INTERFACE TIMING – MASTER MODE BCLK (Output) FRAME (Output) ADCDAT DACDAT Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T =+25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.

  • Page 16: Audio Interface Timing - Slave Mode

    WM8940 AUDIO INTERFACE TIMING – SLAVE MODE BCLK FRAME LRSU DACDAT ADCDAT Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T =+25 C, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER...

  • Page 17: Control Interface Timing - 3-Wire Mode

    WM8940 CONTROL INTERFACE TIMING – 3-WIRE MODE CSB/GPIO SCLK SDIN Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T...

  • Page 18: Control Interface Timing - 2-Wire Mode

    WM8940 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T = +25 C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

  • Page 19: Device Description

    DEVICE DESCRIPTION INTRODUCTION The WM8940 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras or camcorders with mono audio, record and playback capability.

  • Page 20: Control Interfaces

    CONTROL INTERFACES To allow full software control over all its features, the WM8940 supports 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs.
  • Page 21 WM8940 Output from AUX amp AUX2INPPGA R44[2] MICN2INPPGA R44[1] MICN Gain=-12 to +35.25dB MICP2INPPGA R44[0] To input BOOST/mix MICP stage INPPGAVOL R45[5:0] VMID Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input) REGISTER LABEL DEFAULT...

  • Page 22: Input Pga Volume Control

    WM8940 INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are always common and controlled by the register bits INPPGAVOL[5:0].

  • Page 23: Input Boost

    WM8940 In mixer mode (AUXMODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. When used in this mode there will be gain variations through this path from part to part due to the variation of the internal 20kΩ resistors relative to the higher tolerance external resistors.

  • Page 24: Microphone Biasing Circuit

    WM8940 The Auxiliary amplifier path to the BOOST stage is controlled by the AUX2BOOSTVOL[2:0] register bits. When AUX2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.

  • Page 25: Analogue To Digital Converter (Adc)

    Figure 9 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8940 uses a multi-bit, over sampled sigma-delta ADC channel. The use of multi-bit feedback and high over sampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD.

  • Page 26: Selectable High Pass Filter

    WM8940 The ADC is enabled by the ADCEN register bit. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS ADCEN 0 = ADC disabled Power 1 = ADC enabled management 2 Table 11 ADC Enable The polarity of the output signal can also be changed under software control using the ADCPOL register bit.

  • Page 27: Programmable Notch Filters

    WM8940 PROGRAMMABLE NOTCH FILTERS Four programmable notch filters are provided. These filters have a programmable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFx_A0[13:0] and NFx_A1[13:0]. Notch Filter 3 can also be programmed as a 1 order low pass filter.
  • Page 28 WM8940 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS NF2_UP Notch filter 2 update. The notch filter 2 Notch Filter 2A values used internally only update when one of the NFU bits is set high. NF2_EN Notch filter 2 enable. 0=Disabled 1=Enabled 13:0...

  • Page 29: Digital Adc Volume Control

    Table 19 ADC Volume INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8940 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal.
  • Page 30 WM8940 The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode. The ALC/limiter function is enabled by setting the register bit R32[8] ALCSEL. REGISTER LABEL DEFAULT DESCRIPTION ADDRESS R32 (20h) ALCMIN 000 (-12dB) Set minimum gain of PGA...
  • Page 31 WM8940 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS R34 (22h) ALCMODE Determines the ALC mode of operation: ALC Control 3 0 = ALC mode (Normal Operation) 1 = Limiter mode. ALCDCY 0011 Decay (gain ramp-up) time [3:0] (26ms/6dB) (ALCMODE ==0) Per step...

  • Page 32: Normal Mode

    WM8940 NORMAL MODE In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this. Input Signal ALCSEL Gain step Output ALCLVL...

  • Page 33: Attack And Decay Times

    WM8940 Input Signal ALCSEL DCYLIM ATKLIM Gain step Output ALCLVL of PGA Figure 13 ALC Limiter Mode Operation ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing.

  • Page 34: Limiter Mode

    WM8940 ALCMODE = 0 (Normal Mode) Decay Time (s) ALCDCY DCY6dB DCY90% 0000 410µs 3.28ms 23.6ms 0001 820µs 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms 0011 3.28ms 26.2ms 189ms 0100 6.56ms 52.5ms 378ms 0101 13.1ms 105ms 756ms 0110 26.2ms 210ms 1.51s 0111 52.5ms...

  • Page 35: Minimum And Maximum Gain

    WM8940 MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled.

  • Page 36: Alc Hold Time (Normal Mode Only)

    WM8940 ALCMIN Minimum Gain (dB) Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range.
  • Page 37 WM8940 Input Signal Gain Output ALCLVL of PGA Figure 15 ALCLVL Rev 4.4...

  • Page 38: Peak Limiter

    WM8940 Input Signal HOLD Gain Output ALCLVL of PGA Figure 16 ALC Hold Time ALCHLD HOLD 0000 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s Table 27 ALC Hold Time Values...

  • Page 39: Noise Gate (Normal Mode Only)

    When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8940 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH.
  • Page 40 WM8940 Input Signal Gain Output ALCLVL of PGA Figure 17 ALC Operation Above Noise Gate Threshold NGTH Input Signal Gain Output ALCLVL of PGA Figure 18 Noise Gate Operation Rev 4.4...

  • Page 41: Output Signal Path

    Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8940, irrespective of whether the DACs are running or not. The WM8940 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: ▪...

  • Page 42: Hi-Fi Digital To Analogue Converter (Dac)

    Table 32 DAC Auto Mute Control Register DAC OUTPUT LIMITER The WM8940 has a digital output limiter function. The operation of this is shown in Figure 20. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.

  • Page 43: Volume Boost

    WM8940 input Upper Threshold 0.5dB output LIMLVL 0.5dB Lower Threshold -0.5dB -1dB Figure 20 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Table 33, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter.
  • Page 44 WM8940 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS LIMEN Enable the DAC digital limiter: DAC digital 0=disabled limiter control 1 1=enabled LIMDCY 0011 Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms...

  • Page 45: Analogue Outputs

    Table 33 DAC Digital Limiter Control ANALOGUE OUTPUTS The WM8940 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1V rms signals.

  • Page 46: Zero Cross Timeout

    WM8940 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS AUX2SPK Output of auxiliary amplifier to speaker mixer input Speaker mixer control 0 = not selected 1 = selected BYP2SPK Bypass path (output of input boost stage) to speaker mixer input 0 = not selected...

  • Page 47: Mono Mixer And Output

    Table 37 Mono Mixer Control ENABLING THE OUTPUTS Each analogue output of the WM8940 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8940 should remain disabled.

  • Page 48: Unused Analogue Inputs/Outputs

    WM8940 UNUSED ANALOGUE INPUTS/OUTPUTS Whenever an analogue input/output is disabled, it remains connected to AVDD/2 through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up.

  • Page 49: Output Switch

    Table 41 Output Switch Operation (GPIOSEL=001) THERMAL SHUTDOWN The speaker outputs can drive very large currents. To protect the WM8940 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125 C.

  • Page 50: Headphone Output

    WM8940 HEADPHONE OUTPUT The speaker outputs can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC coupled without any capacitor. Headphone Output using DC Blocking Capacitors: DC Coupled Headphone Output: C1 220uF SPKOUTP SPKOUTP WM8940...

  • Page 51: Digital Audio Interfaces

    • BCLK: Bit clock, for synchronisation The clock signals BCLK, and FRAME can be outputs when the WM8940 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: •...
  • Page 52 WM8940 1/fs LEFT RIGHT PHASE PHASE FRAME BCLK DACDAT / n-2 n-1 ADCDAT Figure 26 Right Justified Audio Interface (assuming n-bit word length) In I S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition.

  • Page 53: Audio Interface Control

    WM8940 1/fs 1 BCLK 1 BCLK falling edge can occur anywhere in this area BCLK RIGHT CHANNEL LEFT CHANNEL DACDAT / n-2 n-1 n-2 n-1 ADCDAT Input Word Length (WL) Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1) AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below.
  • Page 54 100=divide by 16 101=divide by 32 110=reserved 111=reserved Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER) Table 44 Clock Control Rev 4.4...

  • Page 55: Loopback

    ADC audio interface. AUDIO SAMPLE RATES The WM8940 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate.
  • Page 56 N controls the ratio of the division, and K the fractional part. The PLL output then passes through a fixed divide by 4, and can also be further divided by MCLKDIV[3:0] (see figure 34). The divided clock (SYSCLK) can be used to clock the WM8940 DSP. REGISTER...

  • Page 57: Integer N Division

    WM8940 INTEGER N DIVISION The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12. If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low power operation.

  • Page 58: Companding

    Table 49 PLL Frequency Examples COMPANDING The WM8940 supports A-law and -law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. If packed mode companding is desired the WL8 register bit is available.
  • Page 59 WM8940 Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) -1 ≤...

  • Page 60: General Purpose Input/Output

    WM8940 A-law Companding Normalised Input Figure 32 A-Law Companding GENERAL PURPOSE INPUT/OUTPUT In 2-wire mode, the CSB pin is not required and it can be used as a GPIO pin. In 3 wire mode, the MODE / GPIO can be configured as a GPIO by setting the MODE_GPIO register bit Whichever pin is used for GPIO, it is controlled from the GPIO control register R8.

  • Page 61: Control Interface

    2 or 3 wire mode as shown in Table 53. The WM8940 is controlled by writing to registers through a serial control interface. A control word consists of 24 bits. The first 7 bits (B23 to B16) are address bits that select which control register is accessed.

  • Page 62: 3-Wire Serial Control Mode

    WM8940 REGISTER LABEL DEFAULT DESCRIPTION ADDRESS MODE_GPIO Selects MODE as a GPIO pin GPIO 0 = MODE is an input. MODE selects 2- wire mode when low and 3-wire mode control when high. 1 = MODE can be an input or output under the control of the GPIO control register.

  • Page 63: 2-Wire Serial Control Mode

    WM8940 acknowledges again by pulling SDIN low for one clock pulse. The controller then sends the third byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8940 acknowledges again by pulling SDIN low for one clock pulse.

  • Page 64: Power Supplies

    PCB to keep digital switching noise out of the analogue signal paths. RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise, it is recommended that the WM8940/WM8941 device is powered up and down using one of the following sequences: Power Up: Turn on external power supplies.
  • Page 65 WM8940 Disable DAC soft mute (DACMU = 0). Power Down: Enable DAC soft mute (DACMU = 1). Enable non-VMID derived bias generator (VMID_OP_EN = 1). Enable on Bias Control (POB_CTRL = 1). Disable analogue amplifier bias control (BIASEN = 0) and VMID (VMIDSEL[1:0] bits set to OFF).

  • Page 66: Power Management

    WM8940 POWER MANAGEMENT VMID The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit.

  • Page 67: Pop Minimisation

    Power-On-Bias Control (POB_CTRL) selects the bias current source for the output stages of the WM8940. 0 selects the VMID derived bias source (normal operation), 1 selects a non-VMID derived source which allows the output amplifiers to be enabled before VMID at start-up. This feature can be used to minimise pops.

  • Page 68: Register Map

    WM8940 REGISTER MAP Rev 4.4...

  • Page 69: Register Bits By Address

    WM8940 REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as “Reserved” should not be changed from the default. REGISTER LABEL DEFAULT DESCRIPTION REFER TO...
  • Page 70 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS MONOEN MONOOUT enable Analogue Outputs 0 = disabled 1 = enabled SPKNEN SPKOUTN enable Analogue Outputs 0 = disabled 1 = enabled SPKPEN SPKOUTP enable Analogue Outputs 0 = disabled 1 = enabled...
  • Page 71 110=reserved 111=reserved Reserved Sets the chip to be master over FRAME and BCLK Digital Audio Interfaces 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER) 7 (07h) 15:7 00000 Reserved Rev 4.4...
  • Page 72 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS POB_CTRL Power on Bias Control POP Minimisation 0=normal (current bias based on VMID) 1=Startup (current bias not based on VMID) SOFT_START VMID Soft Start POP Minimisation 0=disabled 1=enabled TOGGLE Fast VMID Discharge...
  • Page 73 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS DACMU DAC soft mute enable Output Signal Path 0 = DACMU disabled 1 = DACMU enabled Reserved AMUTE DAC auto mute enable Output Signal Path 0 = auto mute disabled 1 = auto mute enabled...
  • Page 74 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 13:0 NF0_A1 0000h Notch Filter 0 a1 coefficient Analogue to Digital Converter (ADC) 18 (12h) NF1_UP Notch filter 1 update. The notch filter 1 values used Analogue to internally only update when one of the NFU bits is set Digital Converter high.
  • Page 75 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 24 (18h) LIMDCY 0011 Output Signal DAC Limiter Decay time (per 6dB gain change) for Path 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms...
  • Page 76 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 31(1Fh) 15:0 0000h Reserved 32 (20h) 15:10 ALCGAIN [5:0] 000000 Readback from this register will return the ALC gain in Input Limiter / this position Automatic Level Control (ALC) Reserved ALCSEL ALC function select...
  • Page 77 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS PLLK[23:18] 001100 Fractional (K) part of PLL1 input/output frequency ratio Master Clock and (treat as one 24-digit binary number). Phase Locked Loop (PLL) 38 (26h) 15:9 Reserved PLLK[17:9] 010010011 Fractional (K) part of PLL1 input/output frequency ratio Master Clock and (treat as one 24-digit binary number).
  • Page 78 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS INPPGAVOL 010000 Input PGA volume Input Signal Path 000000 = -12dB 000001 = -11.25db 010000 = 0dB 111111 = 35.25dB 46 (2Eh) 15:0 0000h Reserved 47 (2Fh) 15:9 Reserved PGABOOST Input Boost...
  • Page 79 WM8940 REGISTER LABEL DEFAULT DESCRIPTION REFER TO ADDRESS 54 (36h) 15:9 Reserved SPKATTN Attenuation control for bypass path (output of input Analogue Outputs boost stage) to speaker mixer input 0 = 0dB 1 = -10dB SPKZC Speaker Volume control zero cross enable:...

  • Page 80: Digital Filter Characteristics

    WM8940 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS UNIT ADC Filter Passband +/- 0.025dB 0.454fs -6dB 0.5fs Passband Ripple +/- 0.025 Stopband 0.546fs Stopband Attenuation f > 0.546fs Group Delay 21/fs ADC High Pass Filter High Pass Filter Corner -3dB Frequency -0.5dB...

  • Page 81: Dac Filter Responses

    WM8940 DAC FILTER RESPONSES 0.15 0.05 -0.05 -0.1 -100 -0.15 -120 -0.2 Frequency (Fs) Frequency (Fs) Figure 39 DAC Digital Filter Ripple Figure 38 DAC Digital Filter Frequency Response ADC FILTER RESPONSES 0.15 0.05 -0.05 -0.1 -100 -0.15 -0.2 -120...

  • Page 82: Highpass Filter

    WM8940 HIGHPASS FILTER The WM8940 has a selectable digital high pass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1 order IIR with a cut-off of around 3.7Hz. In applications mode the filter is a 2 order high pass filter with a selectable cut-off frequency.
  • Page 83 WM8940 (dB) Frequency (Hz) Figure 46 ADC Notch Filter Responses (48kHz); fc=100Hz, 1kHz, 10kHz; fb = 100Hz, 600Hz, 2kHz (dB) Frequency (Hz) Figure 47 ADC Low Pass Filter Responses (48kHz); fc= 1kHz, 5kHz, 10kHz Rev 4.4...

  • Page 84: Notch Filter Worked Example

    WM8940 T T T (dB) Frequency (Hz) Figure 48 Cumulative Notch + Low Pass Filters Responses (48kHz); NF0 fc = 1kHz; NF1 fc = 5kHz; NF2 fc = 10kHz; LPF fc = 11kHz; fb = 100Hz, 600Hz, 2kHz NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth.

  • Page 85: Applications Information

    WM8940 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 49 Recommended External Components Rev 4.4...

  • Page 86: Package Diagram

    WM8940 PACKAGE DIAGRAM FL: 24 PIN QFN PLASTIC PACKAGE 4 0.9 mm BODY, 0.50 mm LEAD PITCH DM102.C DETAIL 1 EXPOSED INDEX AREA GROUND (D/2 X E/2) PADDLE SEE DETAIL 2 TOP VIEW BOTTOM VIEW DETAIL 1 DETAIL 2 0.08...

  • Page 87: Important Notice

    MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. This document is the property of Cirrus Logic, and you may not use this document in connection with any legal analysis concerning Cirrus Logic products described herein. No license to any technology or intellectual property right of Cirrus Logic or any third party is granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property rights.

  • Page 88: Revision History

    WM8940 REVISION HISTORY DATE ORIGINATOR CHANGES 10/05/10 Audio paths diagram updated to correct MONOOUT and SPKOUT paths 26/09/11 JMacD Order codes changed from WM8940GEFL/V and WM8940GEFL/RV to WM8940CGEFL/V and WM8940CGEFL/RV to reflect change to copper wire bonding. 26/09/11 JMacD Package Drawing changed to DM102.C 09/12/21 New order codes added, to reflect PCN-2020-141.

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