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(4) Data hold timing of capture register
If the valid edge is input to the TIn0 pin while 16-bit capture/compare register n1 (CRn1) is being read, CRn1
performs the capture operation, but this capture value is not guaranteed. However, the interrupt request signal
(INTTMn1) is set as a result of detection of the valid edge.
Count pulse
TMn count value
Edge input
Capture read signal
CRn1 interrupt value
Remark n = 0, 1
(5) Setting valid edge
Before setting the valid edge of the TIn0 pin, stop the timer operation by resetting bits 2 and 3 (TMCn2 and
TMCn3) of 16-bit timer mode control register n to 0, 0. Set the valid edge by using bits 4 and 5 (ESn00 and
ESn01) of prescaler mode register n0 (PRMn0).
(6) Re-triggering one-shot pulse
(a) One-shot pulse output by software
When a one-shot pulse is being output, do not set OSPTn to 1. To output a one-shot pulse again, wait until
the interrupt INTTMn0, which occurs on a match with CRn0, or INTTMn1, which occurs on a match with
CRn1, has occurred.
(b) One-shot pulse output with external trigger
If the external trigger occurs while a one-shot pulse is being output, it is ignored.
(c) One-shot pulse output function
When using the one-shot pulse output function of timer 0 or 1 by software trigger, the level of the TIn0 pin or
the pin multiplexed with it must not be changed.
Even in this case, the external trigger remains valid. Consequently, the timer is cleared and started by the
level of the TIn0 pin or the pin multiplexed with it, and a pulse is output when it is not expected.
206
CHAPTER 7
TIMER/COUNTER FUNCTION
Figure 7-34. Data Hold Timing of Capture Register
N
N + 1
INTTMn1
X
Capture operation
User's Manual U13850EJ4V0UM
N + 2
M
M + 1
N+1
A capture operation is performed
but not guaranteed.
M + 2
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