NEC V850/SB1TM User Manual page 207

(7) Operation of OVFn flag
(a) OVFn flag set
The OVFn flag is set to 1 in the following case:
Select a mode in which the timer is cleared and started on a match between TMn and CRn0, a mode in
which it is cleared and started by the valid edge of TIn0, or free-running mode.
↓
Set CRn0 to FFFFH.
↓
When TMn counts up from FFFFH to 0000H
(b) Clear OVFn flag
Even if the OVFn flag is cleared before the next count clock is counted (before TMn become 0001H) after
TMn has overflowed, the OVFn flag is set again and the clear becomes invalid.
(8) Conflict operation
(a) If the read period and capture trigger input conflict
When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, if the read
period and capture trigger input conflict, the capture trigger has priority. The read data of CRn0 and CRn1 is
undefined.
(b) If the match timings of the write period and TMn conflict
When 16-bit capture/compare registers n0 and n1 (CRn0, CRn1) are used as capture registers, because
match detection cannot be performed correctly if the match timings of the write period and 16-bit timer
register n (TMn) conflict, do not write to CRn0 and CRn1 close to the match timing.
(9) Timer operation
(a) CRn1 capture
Even if 16-bit timer register n (TMn) is read, a capture to 16-bit capture/compare register n1 (CRn1) is not
performed.
(b) Acknowledgement of TIn0 and TIn1 pins
When the timer is stopped, input signals to the TIn0 and TIn1 pins are not acknowledged, regardless of the
CPU operation.
CHAPTER 7 TIMER/COUNTER FUNCTION
Figure 7-35. Operation Timing of OVFn Flag
Count pulse
CRn0
FFFFH
TMn
FFFEH FFFFH
OVFn
INTTMn0
Remark n = 0, 1
User's Manual U13850EJ4V0UM
0000H 0001H
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