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19.2 IEBus Controller Configuration
The block diagram of the IEBus controller is shown below.
8
12
BCR(8)
UAR(12)
Internal
registers
8
12
RX
NF
TX
MPX
IEBus interface block
CLK
Bit processing block
(1) Hardware configuration and function
The IEBus mainly consists of the following six internal blocks.
• CPU interface block
• Interrupt control block
• Internal registers
• Bit processing block
• Field processing block
• IEBus interface block
CHAPTER 19
IEBus CONTROLLER (V850/SB2)
Figure 19-10. IEBus Controller Block Diagram
CPU interface block
12
12
8
8
SAR(12)
PAR(12)
CDR(8)
DLR(8)
12
12
8
8
Internal bus
8
MPX
PSR (8 bits)
TX/RX
Parity generation
Contention
error detection
detection
User's Manual U13850EJ4V0UM
8
8
8
8
DR(8)
USR(8)
ISR(8)
SSR(8)
SCR(8)
8
8
8
8
12
8
12-bit latch
Interrupt
controller
Comparator
Interrupt control block
ACK
generation
Field processing block
8
8
CCR(8)
8
8
INT request
(handler, DMA transfer)
5
Internal bus R/W
453
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