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(i)
A16 to A21 (Address 16 to 21) ∙∙∙ output
These comprise an address bus that is used for external access. These pins operate as the higher 6-bit
address output pins within a 22-bit address. The output changes in synchronization with the rising edge
of the clock in the T1 state of the bus cycle. When the timing sets the bus cycle as inactive, the
previous bus cycle's address is retained.
(8) P70 to P77 (Port 7), P80 to P83 (Port 8) ∙∙∙ input
Port 7 is an 8-bit input-only port in which all pins are fixed as input pins. Port 8 is a 4-bit input-only port.
P70 to P77 and P80 to P83 can function as input ports and as analog input pins for the A/D converter. However,
they cannot be switched between these input port and analog input pin.
(a) Port mode
P70 to P77 and P80 to P83 are input-only pins.
(b) Control mode (external expansion mode)
P70 to P77 also function as pins ANI0 to ANI7 and P80 to P83 also function as ANI8 to ANI11, but these
alternate functions are not switchable.
(i)
ANI0 to ANI11 (Analog Input 0 to 11) ∙∙∙ input
These are analog input pins for the A/D converter.
Connect a capacitor between these pins and AV
not apply voltage that is outside the range for AV
the A/D converter. If it is possible for noise above the AV
these pins using a diode that has a small V
(9) P90 to P96 (Port 9) ∙∙∙ 3-state I/O
Port 9 is a 7-bit I/O port in which input and output can be specified in 1-bit units.
P90 to P96 can function as I/O port pins, control signal output pins, and bus hold control signal output pins when
memory is expanded externally.
During 8-bit access of port 9, the highest bit is ignored during a write operation and is read as a "0" during a read
operation.
The I/O signal level uses the bus interface power supply pins BV
(a) Port mode
P90 to P96 can be set in 1-bit units as input or output pins according to the contents of the port 9 mode
register (PM9).
(b) Control mode (external expansion mode)
P90 to P96 can be set to operate as control signal outputs for external memory expansion according to the
contents of the memory expansion register (MM).
(i)
LBEN (Lower Byte Enable) ∙∙∙ output
This is a lower byte enable signal output pin for an external 16-bit data bus. The output changes in
synchronization with the rising edge of the clock in the T1 state of the bus cycle. When the timing sets
the bus cycle as inactive, the previous bus cycle's address is retained.
64
CHAPTER 2
PIN FUNCTIONS
to prevent noise-related operation faults. Also, do
SS
and AV
SS
value.
F
DD
User's Manual U13850EJ4V0UM
to pins that are being used as inputs for
REF
range or below the AV
REF
and BV
as a reference.
SS
to enter, clamp
SS
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