NEC V850/SB1TM User Manual page 507

Instruction Set List (4/4)
Mnemonic
Instruction
Group
Special LDSR reg2, regID rrrrr111111RRRRR
STSR regID, reg2 rrrrr111111RRRRR
TRAP vector
RETI
HALT
DI
EI
NOP
Note The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the
above table. Therefore, the meaning of register specification for mnemonic description and op code is
different from that of the other instructions.
rrr = regID specification
RRRRR = reg2 specification
APPENDIX B
Operand Op Code
0000000000100000
(Note)
0000000001000000
00000111111iiiii
0000000100000000
0000011111100000
0000000101000000
0000011111100000
0000000100100000
0000011111100000
0000000101100000
1000011111100000
0000000101100000
0000000000000000 Uses 1 clock cycle without doing anything
User's Manual U13850EJ4V0UM
INSTRUCTION SET LIST
Operation
SR [regID] ←GR
regID = EIPC, FEPC
[reg2]
regID = EIPSW,
FEPSW
regID = PSW
GR [reg2] ← SR [regID]
← PC + 4 (Restored PC)
EIPC
← PSW
EIPSW
ECR.EICC ← Interrupt code
← 1
PSW.EP
← 1
PSW.ID
PC ← 00000040H (vector = 00H to 0FH)
00000050H (vector = 10H to 1FH)
if PSW.EP = 1
← EIPC
then PC
PSW ← EIPSW
else if PSW.NP = 1
then PC ← FEPC
PSW ← FEPSW
else PC ← EIPC
PSW ← EIPSW
Stops
PSW.ID ← 1
(Maskable interrupt disabled)
PSW.ID ← 0
(Maskable interrupt enabled)
Flag
CY OV S Z SAT
× × × × ×
R R R R R
507