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(2) Asynchronous serial interface status registers 0, 1 (ASIS0, ASIS1)
When a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error.
ASISn can be read using an 8-/1-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 10-34. Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)
After reset: 00H
7
ASISn
0
(n = 0, 1)
PEn
0
1
FEn
0
1
OVEn
0
1
Notes 1. Even if a stop bit length has been set as two bits by setting bit 2 (SLn) in asynchronous serial
interface mode register n (ASIMn), stop bit detection during a receive operation only applies to a
stop bit length of 1 bit.
2. Be sure to read the contents of receive buffer register n (RXBn) when an overrun error has
occurred.
Until the contents of RXBn are read, further overrun errors will occur when receiving data.
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CHAPTER 10
SERIAL INTERFACE FUNCTION
R
Address: FFFFF302H, FFFFF312H
6
5
0
0
No parity error
Parity error
(Transmit data parity does not match)
No framing error
Note 1
Framing error
(Stop bit not detected)
No overrun error
Note 2
Overrun error
(Next receive operation was completed before data was read from receive buffer register)
User's Manual U13850EJ4V0UM
4
3
<2>
0
0
PEn
Parity error flag
Framing error flag
Overrun error flag
<1>
<0>
FEn
OVEn
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