Altera PHY IP Core Transceiver Controller Manuals

Manuals and User Guides for Altera PHY IP Core Transceiver Controller. We have 1 Altera PHY IP Core Transceiver Controller manual available for free PDF download: User Manual

Altera PHY IP Core User Manual

Altera PHY IP Core User Manual (230 pages)

Brand: Altera | Category: Transceiver | Size: 4.12 MB

Table of Contents

Table of Contents
3
Chapter 1. Introduction

9
- Pcs
  10
- Reset Controller
  10
- Pma
  11
- Reset Controller
  11
- Avalon-MM PHY Management
  11
- Running a Simulation Testbench
  12
- Unsupported Features
  13
Chapter 2. Getting Started

15
- Installation and Licensing
  15
- Design Flows
  15
- Megawizard Plug-In Manager Flow
  16
  - Specifying Parameters
    16
  - Simulate the IP Core
    18
Chapter 3. 10GBASE-R PHY IP Core

20
- Release Information
  20
- Device Family Support
  21
- Performance and Resource Utilization
  21
  - Stratix IV Devices
    21
  - Stratix V Devices
    22
- Parameter Settings
  22
  - General Options
    22
  - Analog Options
    23
    
    Stratix IV Devices
    23
    
    Stratix V Devices
    24
- Interfaces
  29
  - Ports
    29
    
    SDR XGMII TX Interface
    30
    
    SDR XGMII RX Interface
    31
    
    Status Interface
    32
    
    Clocks, Reset, and Powerdown
    32
    
    Serial Interface
    35
  - Register Interface
    35
    
    Register Descriptions
    36
  - Dynamic Reconfiguration
    38
    
    Dynamic Reconfiguration for Stratix IV Devices
    38
    
    Dynamic Reconfiguration for Stratix V Devices
    39
- Timequest Timing Constraints
  40
- Simulation Files and Example Testbench
  42
Chapter 4. XAUI PHY IP Core

43
Chapter 5. Interlaken PHY IP Core

67
- Device Family Support
  68
- Parameter Settings
  68
  - General Options
    68
  - Advanced Options
    69
  - Analog Settings
    70
- Interfaces
  74
  - Ports
    74
    
    Avalon-ST TX Interface
    75
    
    Avalon-ST RX Interface
    76
    
    PLL Interface
    78
    
    TX and RX Serial Interface
    78
    
    Optional Clocks for Deskew
    78
  - Registers
    79
    
    Register Descriptions
    79
  - Transceiver Reconfiguration
    81
- Timequest Timing Constraints
  82
- Simulation Files and Example Testbench
  82
Chapter 6. PHY IP Core for PCI Express (PIPE)

83
- Device Family Support
  83
- Resource Utilization
  84
- Parameter Settings
  84
  - General Options
    84
  - Analog Options
    85
- Interfaces
  90
  - Ports
    90
    
    Avalon-ST TX Input Data from the PHYMAC
    91
    
    Avalon-ST RX Output Data to the PHYMAC
    91
    
    PIPE Interface
    92
    
    Transceiver Serial Interface
    94
    
    Optional Status Interface
    94
  - Registers
    95
    
    Register Descriptions
    96
  - Dynamic Reconfiguration
    99
- Simulation Files and Example Testbench
  100
Chapter 7. Custom PHY IP Core

101
- Device Family Support
  102
- Performance and Resource Utilization
  102
- Parameter Settings
  103
  - General Options
    103
  - Word Alignment
    106
  - Rate Match FIFO
    107
  - 8B/10B Encoder and Decoder
    108
  - Byte Ordering
    108
  - PLL Reconfiguration
    109
  - Analog Options
    110
  - Presets for Ethernet
    114
- Interfaces
  115
  - Ports
    115
    
    Avalon-ST TX Input Data from the MAC
    117
    
    Avalon-ST RX Output Data to the MAC
    117
    
    Clock Interface
    118
    
    Transceiver Serial Data Interface
    118
    
    Status Signals (Optional)
    118
    
    Reset Control and Status (Optional)
    119
  - Register Interface
    120
    
    Register Descriptions
    121
  - Dynamic Reconfiguration
    124
- Simulation Files and Example Testbench
  124
Chapter 8. Low Latency PHY IP Core

125
- Device Family Support
  125
- Performance and Resource Utilization
  126
- Parameter Settings
  127
  - General Options
    127
  - Additional Options
    129
  - PLL Reconfiguration Options
    130
  - Analog Options
    132
- Interfaces
  136
  - Ports
    136
    
    Avalon-ST TX and RX Data Interface to the FPGA Fabric
    137
    
    Serial Data Interface
    137
    
    Optional Status Interface
    138
    
    Clock Interface
    138
    
    Reset Control and Status (Optional)
    138
  - Register Interface
    139
    
    Register Descriptions
    140
  - Dynamic Reconfiguration
    141
- Simulation Files and Example Testbench
  141
Chapter 9. Deterministic Latency PHY IP Core

143
- Auto-Negotiation
  144
- Achieving Deterministic Latency
  145
  - Delay Estimation Logic
    145
  - Delay Numbers
    146
- Device Family Support
  147
- Parameter Settings
  148
  - General Options
    148
  - Additional Options
    150
  - Analog Options
    151
- Interfaces
  156
  - Ports
    156
    
    Avalon-ST TX Input Data from the MAC
    158
    
    Avalon-ST RX Output Data to the MAC
    158
    
    Clock Interface
    158
    
    Transceiver Serial Data Interface
    159
    
    TX and RX Status Signals
    159
    
    Optional Reset Control and Status
    160
  - Register Interface
    160
    
    Register Descriptions
    162
  - Dynamic Reconfiguration
    164
- Channel Placement and Utilization
  165
- Simulation Files and Example Testbench
  166
Chapter 10. Transceiver Reconfiguration Controller

167
- System Overview
  169
- Device Family Support
  170
- Performance and Resource Utilization
  171
- Parameter Settings
  171
- Interfaces
  173
- Reconfiguration Controller Memory Map
  175
- Transceiver Calibration Functions
  176
  - Offset Cancellation
    176
  - Duty Cycle Calibration
    176
  - Auxiliary Transmit (ATX) PLL Calibration
    176
- PMA Analog Controls
  177
- Eyeq
  178
- Dfe
  180
- Aeq
  182
- ATX PLL Calibration
  183
- PLL Reconfiguration
  184
- Channel and PLL Reconfiguration
  187
  - Channel Reconfiguration
    187
  - PLL Reconfiguration
    188
- Streamer Module
  188
  - Mode 0 Streaming a MIF for Reconfiguration
    190
  - Mode 1 Avalon-MM Direct Writes for Reconfiguration
    191
  - Stratix V MIF
    191
    
    MIF Format
    191
- Procedures for Reconfiguration
  193
  - Changing Transceiver Settings Using Register-Based Reconfiguration
    193
    
    Register-Based Write
    193
    
    Register-Based Read
    193
  - Changing Transceiver Settings Using Streamer-Based Reconfiguration
    194
    
    Streamer Based Reconfiguration
    194
    
    Direct Write Reconfiguration
    195
- Understanding Logical Channel Numbering
  197
- Reconfiguration Controller to PHY IP Connectivity
  203
- Merging TX Plls in Multiple Transceiver PHY Instances
  204
- Loopback Modes
  205
Chapter 11. Migrating from Stratix IV to Stratix V Devices

208
- Dynamic Reconfiguration of Transceivers
  208
  - Dynamic Reconfiguration for Stratix V Transceivers
    208
  - Dynamic Reconfiguration for Stratix IV Transceivers
    208
- Xaui Phy
  209
  - Parameter Differences
    209
  - Port Differences
    210
- PHY IP Core for PCI Express PHY (PIPE)
  212
  - Parameter Differences
    212
  - Port Differences
    213
- Custom PHY
  216
  - Parameter Differences
    216
  - Port Differences
    217
Additional Information

219
- Revision History
  219
- How to Contact Altera
  228
- Typographic Conventions
  228

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