Figure 12-2. Spi Connections; Figure 12-3. Basic Spi Initiator And Target Connections - Nvidia Jetson Orin NX Design Manual

Figure 12-2. SPI Connections
Jetson
SoC – SPI
GP47_SPI1_SCK
GP48_SPI1_MISO
GP49_SPI1_MOSI
GP50_SPI1_CS0
GP51_SPI1_CS1
GP36_SPI3_SCK
GP37_SPI3_MISO
GP38_SPI3_MOSI
GP39_SPI3_CS0
GP40_SPI3_CS1
Figure 12-3. Basic SPI Initiator and Target Connections
Jetson Initiator
SPIn_CSx
SPIn_SCK
SPIn_MOSI
SPIn_MISO
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
SPI0_SCK
91
SPI0_MISO
93
SPI0_MOSI
89
SPI0_CS0*
95
SPI0_CS1*
97
SPI1_SCK
106
SPI_MISO
108
SPI1_MOSI
104
SPI1_CS0*
110
SPI1_CS1*
112
SPI Target
CS (Chip Select)
CLK (Clock)
MOSI (Master out, Slave in)
MISO (Master in, Slave out)
Connect to up to 2 SPI
devices (separate CS
for each)
Connect to up to 2 SPI
devices (separate CS
for each)
Jetson Target
SPIn_CSx
SPIn_SCK
SPIn_MOSI
SPIn_MISO
Miscellaneous Interfaces
SPI Initiator
CS (Chip Select)
CLK (Clock)
MOSI (Master out, Slave in)
MISO (Master in, Slave out)
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