Figure 9-4. S-Parameter Up To Hbr2; Figure 9-5. S-Parameter Up To Hbr3 - Nvidia Jetson Orin NX Design Manual

Parameter
Connector
Voiding
RBR/HBR
HBR2/HBR3
General
Keep critical PCIe traces away from other signal traces or unrelated power traces/areas or power supply components
Notes:
1. For eDP and DP, the specification puts a higher priority on the trace loss characteristic than on the impedance. However, before
selecting 85 Ω for impedance, it is important to make sure the selected stack-up, material and trace dimension can achieve the
needed low loss characteristic.
2. The average of the differential signals is used for length and delay matching.
3. Do not perform length and delay matching within breakout region. Recommend doing trace length and delay matching to <1ps
before vias or any discontinuity to minimize common mode conversion.
The following figures show the eDP and DP interface signal routing requirements.
Figure 9-4. S-Parameter Up to HBR2
Figure 9-5. S-Parameter Up to HBR3
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Requirement Units
No requirement
Voiding required
Display
Notes
HBR2: Standard DP Connector: Voiding
requirement is stack-up dependent. For
typical stack-ups, voiding on the layer under
the connector pad is required to be 5.7 mil
larger than the connector pad.
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