Edp And Dp; Figure 9-1. Dp And Edp Connection Example; Table 9-2. Dp And Hdmi Pin Mapping - Nvidia Jetson Orin NX Design Manual

Table 9-2. DP and HDMI Pin Mapping
Module Pin Name
DP1_TXD3_P
DP1_TXD3_N
DP1_TXD2_P
DP1_TXD2_N
DP1_TXD1_P
DP1_TXD1_N
DP1_TXD0_P
DP1_TXD0_N
9.1

eDP and DP

The following figure shows a basic the DP and eDP connection example.
Figure 9-1. DP and eDP Connection Example
Jetson
SoC – DP/HDMI
GP74_HPD0_N
SF_DPAUX01_P
SF_DPAUX01_N
HS_DISP0_HDMI_CK_DP3_P
HS_DISP0_HDMI_CK_DP3_N
HS_DISP0_HDMI_D0_DP2_P
HS_DISP0_HDMI_D0_DP2_N
HS_DISP0_HDMI_D1_DP1_P
HS_DISP0_HDMI_D1_DP1_N
HS_DISP0_HDMI_D2_DP0_P
HS_DISP0_HDMI_D2_DP0_N
Notes:
1. Level shifter required on DP0_HPD to avoid the pin from being driven when Jetson Orin NX is
off. The level shifter must be non-inverting (preserve the polarity of the HPD signal from the
display). The reference design uses a BJT level shifter, and a resistor divider is needed. See
the reference design if a similar approach will be used.
2. Load Switch enable is from powergood pin of main 3.3V supply.
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Module Pin #s
83
81
77
75
71
69
65
63
VDD_3V3_SYS
VDD_1V8
BUCK_3V3_PG
Level Shifter
DP1_HPD
96 1.8V
0.1uF
DP1_AUX_N
98
DP1_AUX_P
100
0.1uF
0.1uF
DP1_TXD3_N
81
DP1_TXD3_P
83
0.1uF
0.1uF
DP1_TXD2_N
75
DP1_TXD2_P
77
0.1uF
0.1uF
DP1_TXD1_N
69
DP1_TXD1_P
71
0.1uF
0.1uF
DP1_TXD0_N
63
DP1_TXD0_P
65
0.1uF
HDMI DP
TXC+ TX3+
TXC – TX3–
TX0+ TX2+
TX0– TX2–
TX1+ TX1+
TX1– TX1–
TX2+ TX0+
TX2– TX0–
VDD_3V3_EDP
Load Switch
IN OUT
EN
3.3V
VDD_3V3_SYS
0.1uF
Display
DP
Conn
.
PWR
20
PWR_RET
19
HPD
18
AUXN
17
GND
16
AUXP
15
CEC_DP
14
MODE
13
LANE_3N
12
GND
11
LANE_3P
10
LANE_2N
9
GND
8
LANE_2P
7
LANE_1N
6
GND
5
LANE_1P
4
LANE_0N
3
GND
2
LANE_0P
1
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